diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 18 |
4 files changed, 33 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 1fe4bb57c5a..7039174e078 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1055,6 +1055,15 @@ enum opcode { * - src1 is the destination register when write commit occurs. */ GS_OPCODE_SVB_WRITE, + + /** + * Set destination index in the SVB write message payload (M0.5). Used + * in gen6 for transform feedback. + * + * - dst is the header to save the destination indices for SVB WRITE. + * - src is the register that holds the destination indices value. + */ + GS_OPCODE_SVB_SET_DST_INDEX, }; enum brw_derivative_quality { diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 45e126f98c0..25f73356421 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -530,6 +530,8 @@ brw_instruction_name(enum opcode op) return "set_primitive_id"; case GS_OPCODE_SVB_WRITE: return "gs_svb_write"; + case GS_OPCODE_SVB_SET_DST_INDEX: + return "gs_svb_set_dst_index"; default: /* Yes, this leaks. It's in debug code, it should never occur, and if diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 8391319517c..2a2f7752c15 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -222,6 +222,7 @@ public: unsigned sol_binding; /**< gen6: SOL binding table index */ bool sol_final_write; /**< gen6: send commit message */ + unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */ bool is_send_from_grf(); bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask); @@ -661,6 +662,9 @@ private: struct brw_reg dst, struct brw_reg src0, struct brw_reg src1); + void generate_gs_svb_set_destination_index(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src); void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src); void generate_gs_prepare_channel_masks(struct brw_reg dst); void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index db936206aa2..226968b2094 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -612,6 +612,20 @@ vec4_generator::generate_gs_svb_write(vec4_instruction *inst, } void +vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src) +{ + + int vertex = inst->sol_vertex; + brw_push_insn_state(p); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex)); + brw_pop_insn_state(p); +} + +void vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src) { brw_push_insn_state(p); @@ -1389,6 +1403,10 @@ vec4_generator::generate_code(const cfg_t *cfg) generate_gs_svb_write(inst, dst, src[0], src[1]); break; + case GS_OPCODE_SVB_SET_DST_INDEX: + generate_gs_svb_set_destination_index(inst, dst, src[0]); + break; + case GS_OPCODE_THREAD_END: generate_gs_thread_end(inst); break; |