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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 270cdf29db3..105fff3548f 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1688,6 +1688,9 @@ enum brw_pixel_shader_coverage_mask_mode {
# define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25
# define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
+#define GEN10_CACHE_MODE_SS 0x0e420
+#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
#define INSTPM 0x20c0
# define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9e1cf54abda..9e64213c2e7 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -62,6 +62,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_upload_invariant_state(brw);
+ if (devinfo->gen == 10) {
+ brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
+ REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+ GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+ }
+
if (devinfo->gen == 9) {
/* Recommended optimizations for Victim Cache eviction and floating
* point blending.