diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_ds_state.c | 65 |
1 files changed, 54 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c index 2b743f6cd95..30deabb06ed 100644 --- a/src/mesa/drivers/dri/i965/gen7_ds_state.c +++ b/src/mesa/drivers/dri/i965/gen7_ds_state.c @@ -58,21 +58,64 @@ const struct brw_tracked_state gen7_tes_push_constants = { static void gen7_upload_ds_state(struct brw_context *brw) { - /* Disable the DS Unit */ - BEGIN_BATCH(6); - OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); + const struct brw_stage_state *stage_state = &brw->tes.base; + /* BRW_NEW_TESS_PROGRAMS */ + bool active = brw->tess_eval_program; + + /* BRW_NEW_TES_PROG_DATA */ + const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data; + const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base; + const struct brw_stage_prog_data *prog_data = &vue_prog_data->base; + + const unsigned thread_count = (brw->max_ds_threads - 1) << + (brw->is_haswell ? HSW_DS_MAX_THREADS_SHIFT : GEN7_DS_MAX_THREADS_SHIFT); + + if (active) { + BEGIN_BATCH(6); + OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); + OUT_BATCH(stage_state->prog_offset); + OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), + GEN7_DS_SAMPLER_COUNT) | + SET_FIELD(prog_data->binding_table.size_bytes / 4, + GEN7_DS_BINDING_TABLE_ENTRY_COUNT)); + if (prog_data->total_scratch) { + OUT_RELOC(stage_state->scratch_bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + ffs(prog_data->total_scratch) - 11); + } else { + OUT_BATCH(0); + } + OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg, + GEN7_DS_DISPATCH_START_GRF) | + SET_FIELD(vue_prog_data->urb_read_length, + GEN7_DS_URB_READ_LENGTH)); + + OUT_BATCH(GEN7_DS_ENABLE | + GEN7_DS_STATISTICS_ENABLE | + thread_count | + (tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ? + GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0)); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(6); + OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } + brw->tes.enabled = active; } const struct brw_tracked_state gen7_ds_state = { .dirty = { - .mesa = 0, - .brw = BRW_NEW_CONTEXT, + .mesa = _NEW_TRANSFORM, + .brw = BRW_NEW_BATCH | + BRW_NEW_CONTEXT | + BRW_NEW_TESS_PROGRAMS | + BRW_NEW_TES_PROG_DATA, }, .emit = gen7_upload_ds_state, }; |