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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp6
-rw-r--r--src/mesa/drivers/dri/i965/brw_nir.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.cpp12
-rw-r--r--src/mesa/drivers/dri/i965/brw_tcs.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp14
-rw-r--r--src/mesa/main/shaderapi.c10
-rw-r--r--src/mesa/program/prog_statevars.c2
-rw-r--r--src/mesa/state_tracker/st_program.c12
8 files changed, 34 insertions, 32 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 03f9c24d151..b1f9f639c41 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5925,15 +5925,15 @@ fs_visitor::run_tcs_single_patch()
}
/* Fix the disptach mask */
- if (nir->info->tcs.vertices_out % 8) {
+ if (nir->info->tess.tcs_vertices_out % 8) {
bld.CMP(bld.null_reg_ud(), invocation_id,
- brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L);
+ brw_imm_ud(nir->info->tess.tcs_vertices_out), BRW_CONDITIONAL_L);
bld.IF(BRW_PREDICATE_NORMAL);
}
emit_nir_code();
- if (nir->info->tcs.vertices_out % 8) {
+ if (nir->info->tess.tcs_vertices_out % 8) {
bld.emit(BRW_OPCODE_ENDIF);
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index 2d2fce28eef..474449818c7 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -336,7 +336,7 @@ brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
nir_builder_init(&b, function->impl);
nir_foreach_block(block, function->impl) {
remap_patch_urb_offsets(block, &b, vue_map,
- nir->info->tes.primitive_mode);
+ nir->info->tess.primitive_mode);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index fb4cde98a1f..f0da4b71f3e 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1351,9 +1351,9 @@ brw_compile_tes(const struct brw_compiler *compiler,
TESS_SPACING_FRACTIONAL_EVEN - 1);
prog_data->partitioning =
- (enum brw_tess_partitioning) (nir->info->tes.spacing - 1);
+ (enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
- switch (nir->info->tes.primitive_mode) {
+ switch (nir->info->tess.primitive_mode) {
case GL_QUADS:
prog_data->domain = BRW_TESS_DOMAIN_QUAD;
break;
@@ -1367,15 +1367,15 @@ brw_compile_tes(const struct brw_compiler *compiler,
unreachable("invalid domain shader primitive mode");
}
- if (nir->info->tes.point_mode) {
+ if (nir->info->tess.point_mode) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
- } else if (nir->info->tes.primitive_mode == GL_ISOLINES) {
+ } else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
} else {
/* Hardware winding order is backwards from OpenGL */
prog_data->output_topology =
- nir->info->tes.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
- : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
+ nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
+ : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
}
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 9e9d9eb00d2..78ad257e3b9 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -54,7 +54,7 @@ create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
nir->info->inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
nir->info->outputs_written = key->outputs_written;
- nir->info->tcs.vertices_out = key->input_vertices;
+ nir->info->tess.tcs_vertices_out = key->input_vertices;
nir->info->name = ralloc_strdup(nir, "passthrough");
nir->num_uniforms = 8 * sizeof(uint32_t);
@@ -328,10 +328,10 @@ brw_tcs_populate_key(struct brw_context *brw,
/* We need to specialize our code generation for tessellation levels
* based on the domain the DS is expecting to tessellate.
*/
- key->tes_primitive_mode = tep->program.info.tes.primitive_mode;
+ key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
key->quads_workaround = brw->gen < 9 &&
- tep->program.info.tes.primitive_mode == GL_QUADS &&
- tep->program.info.tes.spacing == TESS_SPACING_EQUAL;
+ tep->program.info.tess.primitive_mode == GL_QUADS &&
+ tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
if (tcp) {
key->program_string_id = tcp->id;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 9ef3dc04665..3ea90107f76 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
@@ -94,9 +94,10 @@ vec4_tcs_visitor::emit_prolog()
* HS instance dispatched will only have its bottom half doing real
* work, and so we need to disable the upper half:
*/
- if (nir->info->tcs.vertices_out % 2) {
+ if (nir->info->tess.tcs_vertices_out % 2) {
emit(CMP(dst_null_d(), invocation_id,
- brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L));
+ brw_imm_ud(nir->info->tess.tcs_vertices_out),
+ BRW_CONDITIONAL_L));
/* Matching ENDIF is in emit_thread_end() */
emit(IF(BRW_PREDICATE_NORMAL));
@@ -110,7 +111,7 @@ vec4_tcs_visitor::emit_thread_end()
vec4_instruction *inst;
current_annotation = "thread end";
- if (nir->info->tcs.vertices_out % 2) {
+ if (nir->info->tess.tcs_vertices_out % 2) {
emit(BRW_OPCODE_ENDIF);
}
@@ -420,9 +421,9 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir = brw_postprocess_nir(nir, compiler, is_scalar);
if (is_scalar)
- prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 8);
+ prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 8);
else
- prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 2);
+ prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 2);
/* Compute URB entry size. The maximum allowed URB entry size is 32k.
* That divides up as follows:
@@ -441,7 +442,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
unsigned output_size_bytes = 0;
/* Note that the patch header is counted in num_per_patch_slots. */
output_size_bytes += num_per_patch_slots * 16;
- output_size_bytes += nir->info->tcs.vertices_out * num_per_vertex_slots * 16;
+ output_size_bytes += nir->info->tess.tcs_vertices_out *
+ num_per_vertex_slots * 16;
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index e67dc52c156..fe4cf1bed22 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -2183,14 +2183,14 @@ _mesa_copy_linked_program_data(const struct gl_shader_program *src,
dst->CullDistanceArraySize = src->Vert.CullDistanceArraySize;
break;
case MESA_SHADER_TESS_CTRL: {
- dst->info.tcs.vertices_out = dst_sh->info.TessCtrl.VerticesOut;
+ dst->info.tess.tcs_vertices_out = dst_sh->info.TessCtrl.VerticesOut;
break;
}
case MESA_SHADER_TESS_EVAL: {
- dst->info.tes.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
- dst->info.tes.spacing = dst_sh->info.TessEval.Spacing;
- dst->info.tes.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
- dst->info.tes.point_mode = dst_sh->info.TessEval.PointMode;
+ dst->info.tess.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
+ dst->info.tess.spacing = dst_sh->info.TessEval.Spacing;
+ dst->info.tess.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
+ dst->info.tess.point_mode = dst_sh->info.TessEval.PointMode;
dst->ClipDistanceArraySize = src->TessEval.ClipDistanceArraySize;
dst->CullDistanceArraySize = src->TessEval.CullDistanceArraySize;
break;
diff --git a/src/mesa/program/prog_statevars.c b/src/mesa/program/prog_statevars.c
index 22527a0184f..5b073ac34bb 100644
--- a/src/mesa/program/prog_statevars.c
+++ b/src/mesa/program/prog_statevars.c
@@ -610,7 +610,7 @@ _mesa_fetch_state(struct gl_context *ctx, const gl_state_index state[],
case STATE_TES_PATCH_VERTICES_IN:
if (ctx->TessCtrlProgram._Current)
- val[0].i = ctx->TessCtrlProgram._Current->info.tcs.vertices_out;
+ val[0].i = ctx->TessCtrlProgram._Current->info.tess.tcs_vertices_out;
else
val[0].i = ctx->TessCtrlProgram.patch_vertices;
return;
diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c
index 96c6bb3fcf8..e1242795670 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -1577,7 +1577,7 @@ st_translate_tessctrl_program(struct st_context *st,
return false;
ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT,
- sttcp->Base.info.tcs.vertices_out);
+ sttcp->Base.info.tess.tcs_vertices_out);
st_translate_program_common(st, &sttcp->Base, sttcp->glsl_to_tgsi, ureg,
PIPE_SHADER_TESS_CTRL, &sttcp->tgsi);
@@ -1601,11 +1601,11 @@ st_translate_tesseval_program(struct st_context *st,
if (ureg == NULL)
return false;
- if (sttep->Base.info.tes.primitive_mode == GL_ISOLINES)
+ if (sttep->Base.info.tess.primitive_mode == GL_ISOLINES)
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE, GL_LINES);
else
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE,
- sttep->Base.info.tes.primitive_mode);
+ sttep->Base.info.tess.primitive_mode);
STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
@@ -1614,12 +1614,12 @@ st_translate_tesseval_program(struct st_context *st,
PIPE_TESS_SPACING_FRACTIONAL_EVEN);
ureg_property(ureg, TGSI_PROPERTY_TES_SPACING,
- (sttep->Base.info.tes.spacing + 1) % 3);
+ (sttep->Base.info.tess.spacing + 1) % 3);
ureg_property(ureg, TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
- !sttep->Base.info.tes.ccw);
+ !sttep->Base.info.tess.ccw);
ureg_property(ureg, TGSI_PROPERTY_TES_POINT_MODE,
- sttep->Base.info.tes.point_mode);
+ sttep->Base.info.tess.point_mode);
st_translate_program_common(st, &sttep->Base, sttep->glsl_to_tgsi,
ureg, PIPE_SHADER_TESS_EVAL, &sttep->tgsi);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 22:03:17 +0000