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-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c3
2 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index b94e9d10db9..618fe59fb67 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -664,6 +664,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t tile_mask_x, tile_mask_y;
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
uint32_t surftype;
+ unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
brw_get_depthstencil_tile_masks(params->depth.mt,
@@ -680,6 +681,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
+ depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index e460ccca513..f0f8b5dcc67 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -44,6 +44,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
+ unsigned int depth = 1;
GLenum gl_target = GL_TEXTURE_2D;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
@@ -56,6 +57,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
rb = (struct gl_renderbuffer*) irb;
if (rb) {
+ depth = MAX2(rb->Depth, 1);
if (rb->TexImage)
gl_target = rb->TexImage->TexObject->Target;
}
@@ -69,6 +71,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
+ depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);