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-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.h2
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h52
2 files changed, 29 insertions, 25 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 50d0d28f7a8..d2744e44ac2 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -13,6 +13,8 @@ extern "C" {
#define BATCH_RESERVED 16
+struct intel_batchbuffer;
+
void intel_batchbuffer_init(struct intel_context *intel);
void intel_batchbuffer_reset(struct intel_context *intel);
void intel_batchbuffer_free(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 63dba897f79..065f1d6d01a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -116,6 +116,32 @@ struct intel_sync_object {
struct brw_context;
+struct intel_batchbuffer {
+ /** Current batchbuffer being queued up. */
+ drm_intel_bo *bo;
+ /** Last BO submitted to the hardware. Used for glFinish(). */
+ drm_intel_bo *last_bo;
+ /** BO for post-sync nonzero writes for gen6 workaround. */
+ drm_intel_bo *workaround_bo;
+ bool need_workaround_flush;
+
+ struct cached_batch_item *cached_items;
+
+ uint16_t emit, total;
+ uint16_t used, reserved_space;
+ uint32_t map[8192];
+#define BATCH_SZ (8192*sizeof(uint32_t))
+
+ uint32_t state_batch_offset;
+ bool is_blit;
+ bool needs_sol_reset;
+
+ struct {
+ uint16_t used;
+ int reloc_count;
+ } saved;
+};
+
/**
* intel_context is derived from Mesa's context class: struct gl_context.
*/
@@ -218,31 +244,7 @@ struct intel_context
int urb_size;
- struct intel_batchbuffer {
- /** Current batchbuffer being queued up. */
- drm_intel_bo *bo;
- /** Last BO submitted to the hardware. Used for glFinish(). */
- drm_intel_bo *last_bo;
- /** BO for post-sync nonzero writes for gen6 workaround. */
- drm_intel_bo *workaround_bo;
- bool need_workaround_flush;
-
- struct cached_batch_item *cached_items;
-
- uint16_t emit, total;
- uint16_t used, reserved_space;
- uint32_t map[8192];
-#define BATCH_SZ (8192*sizeof(uint32_t))
-
- uint32_t state_batch_offset;
- bool is_blit;
- bool needs_sol_reset;
-
- struct {
- uint16_t used;
- int reloc_count;
- } saved;
- } batch;
+ struct intel_batchbuffer batch;
drm_intel_bo *first_post_swapbuffers_batch;
bool need_throttle;