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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h16
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp34
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h16
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_emit.cpp34
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp16
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp20
6 files changed, 68 insertions, 68 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index fe5d29c4328..da8d016da42 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -616,14 +616,14 @@ enum opcode {
* instructions.
*/
FS_OPCODE_FB_WRITE = 128,
- FS_OPCODE_RCP,
- FS_OPCODE_RSQ,
- FS_OPCODE_SQRT,
- FS_OPCODE_EXP2,
- FS_OPCODE_LOG2,
- FS_OPCODE_POW,
- FS_OPCODE_SIN,
- FS_OPCODE_COS,
+ SHADER_OPCODE_RCP,
+ SHADER_OPCODE_RSQ,
+ SHADER_OPCODE_SQRT,
+ SHADER_OPCODE_EXP2,
+ SHADER_OPCODE_LOG2,
+ SHADER_OPCODE_POW,
+ SHADER_OPCODE_SIN,
+ SHADER_OPCODE_COS,
FS_OPCODE_DDX,
FS_OPCODE_DDY,
FS_OPCODE_PIXEL_X,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a0d75cc6f96..693ef0ce31a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -143,15 +143,15 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
return 0;
switch (inst->opcode) {
- case FS_OPCODE_RCP:
- case FS_OPCODE_RSQ:
- case FS_OPCODE_SQRT:
- case FS_OPCODE_EXP2:
- case FS_OPCODE_LOG2:
- case FS_OPCODE_SIN:
- case FS_OPCODE_COS:
+ case SHADER_OPCODE_RCP:
+ case SHADER_OPCODE_RSQ:
+ case SHADER_OPCODE_SQRT:
+ case SHADER_OPCODE_EXP2:
+ case SHADER_OPCODE_LOG2:
+ case SHADER_OPCODE_SIN:
+ case SHADER_OPCODE_COS:
return 1 * c->dispatch_width / 8;
- case FS_OPCODE_POW:
+ case SHADER_OPCODE_POW:
return 2 * c->dispatch_width / 8;
case FS_OPCODE_TEX:
case FS_OPCODE_TXB:
@@ -525,13 +525,13 @@ fs_inst *
fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
{
switch (opcode) {
- case FS_OPCODE_RCP:
- case FS_OPCODE_RSQ:
- case FS_OPCODE_SQRT:
- case FS_OPCODE_EXP2:
- case FS_OPCODE_LOG2:
- case FS_OPCODE_SIN:
- case FS_OPCODE_COS:
+ case SHADER_OPCODE_RCP:
+ case SHADER_OPCODE_RSQ:
+ case SHADER_OPCODE_SQRT:
+ case SHADER_OPCODE_EXP2:
+ case SHADER_OPCODE_LOG2:
+ case SHADER_OPCODE_SIN:
+ case SHADER_OPCODE_COS:
break;
default:
assert(!"not reached: bad math opcode");
@@ -570,7 +570,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
int base_mrf = 2;
fs_inst *inst;
- assert(opcode == FS_OPCODE_POW);
+ assert(opcode == SHADER_OPCODE_POW);
if (intel->gen >= 6) {
/* Can't do hstride == 0 args to gen6 math, so expand it out.
@@ -1135,7 +1135,7 @@ fs_visitor::propagate_constants()
}
break;
- case FS_OPCODE_RCP:
+ case SHADER_OPCODE_RCP:
/* The hardware doesn't do math on immediate values
* (because why are you doing that, seriously?), but
* the correct answer is to just constant fold it
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index d207ac27aa2..94af0e1af16 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -296,14 +296,14 @@ public:
bool is_math()
{
- return (opcode == FS_OPCODE_RCP ||
- opcode == FS_OPCODE_RSQ ||
- opcode == FS_OPCODE_SQRT ||
- opcode == FS_OPCODE_EXP2 ||
- opcode == FS_OPCODE_LOG2 ||
- opcode == FS_OPCODE_SIN ||
- opcode == FS_OPCODE_COS ||
- opcode == FS_OPCODE_POW);
+ return (opcode == SHADER_OPCODE_RCP ||
+ opcode == SHADER_OPCODE_RSQ ||
+ opcode == SHADER_OPCODE_SQRT ||
+ opcode == SHADER_OPCODE_EXP2 ||
+ opcode == SHADER_OPCODE_LOG2 ||
+ opcode == SHADER_OPCODE_SIN ||
+ opcode == SHADER_OPCODE_COS ||
+ opcode == SHADER_OPCODE_POW);
}
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 529df0880f0..285ba46bd46 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -149,28 +149,28 @@ fs_visitor::generate_math(fs_inst *inst,
int op;
switch (inst->opcode) {
- case FS_OPCODE_RCP:
+ case SHADER_OPCODE_RCP:
op = BRW_MATH_FUNCTION_INV;
break;
- case FS_OPCODE_RSQ:
+ case SHADER_OPCODE_RSQ:
op = BRW_MATH_FUNCTION_RSQ;
break;
- case FS_OPCODE_SQRT:
+ case SHADER_OPCODE_SQRT:
op = BRW_MATH_FUNCTION_SQRT;
break;
- case FS_OPCODE_EXP2:
+ case SHADER_OPCODE_EXP2:
op = BRW_MATH_FUNCTION_EXP;
break;
- case FS_OPCODE_LOG2:
+ case SHADER_OPCODE_LOG2:
op = BRW_MATH_FUNCTION_LOG;
break;
- case FS_OPCODE_POW:
+ case SHADER_OPCODE_POW:
op = BRW_MATH_FUNCTION_POW;
break;
- case FS_OPCODE_SIN:
+ case SHADER_OPCODE_SIN:
op = BRW_MATH_FUNCTION_SIN;
break;
- case FS_OPCODE_COS:
+ case SHADER_OPCODE_COS:
op = BRW_MATH_FUNCTION_COS;
break;
default:
@@ -182,7 +182,7 @@ fs_visitor::generate_math(fs_inst *inst,
if (intel->gen >= 6) {
assert(inst->mlen == 0);
- if (inst->opcode == FS_OPCODE_POW) {
+ if (inst->opcode == SHADER_OPCODE_POW) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_math2(p, dst, op, src[0], src[1]);
@@ -775,14 +775,14 @@ fs_visitor::generate_code()
}
break;
- case FS_OPCODE_RCP:
- case FS_OPCODE_RSQ:
- case FS_OPCODE_SQRT:
- case FS_OPCODE_EXP2:
- case FS_OPCODE_LOG2:
- case FS_OPCODE_POW:
- case FS_OPCODE_SIN:
- case FS_OPCODE_COS:
+ case SHADER_OPCODE_RCP:
+ case SHADER_OPCODE_RSQ:
+ case SHADER_OPCODE_SQRT:
+ case SHADER_OPCODE_EXP2:
+ case SHADER_OPCODE_LOG2:
+ case SHADER_OPCODE_POW:
+ case SHADER_OPCODE_SIN:
+ case SHADER_OPCODE_COS:
generate_math(inst, dst, src);
break;
case FS_OPCODE_PIXEL_X:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
index 965a5b333a2..0ea4e5c36f0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
@@ -69,26 +69,26 @@ public:
int math_latency = 22;
switch (inst->opcode) {
- case FS_OPCODE_RCP:
+ case SHADER_OPCODE_RCP:
this->latency = 1 * chans * math_latency;
break;
- case FS_OPCODE_RSQ:
+ case SHADER_OPCODE_RSQ:
this->latency = 2 * chans * math_latency;
break;
- case FS_OPCODE_SQRT:
- case FS_OPCODE_LOG2:
+ case SHADER_OPCODE_SQRT:
+ case SHADER_OPCODE_LOG2:
/* full precision log. partial is 2. */
this->latency = 3 * chans * math_latency;
break;
- case FS_OPCODE_EXP2:
+ case SHADER_OPCODE_EXP2:
/* full precision. partial is 3, same throughput. */
this->latency = 4 * chans * math_latency;
break;
- case FS_OPCODE_POW:
+ case SHADER_OPCODE_POW:
this->latency = 8 * chans * math_latency;
break;
- case FS_OPCODE_SIN:
- case FS_OPCODE_COS:
+ case SHADER_OPCODE_SIN:
+ case SHADER_OPCODE_COS:
/* minimum latency, max is 12 rounds. */
this->latency = 5 * chans * math_latency;
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 2e3f9be75b4..8b4f5bbac15 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -250,14 +250,14 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_unop_rcp:
- emit_math(FS_OPCODE_RCP, this->result, op[0]);
+ emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
break;
case ir_unop_exp2:
- emit_math(FS_OPCODE_EXP2, this->result, op[0]);
+ emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
break;
case ir_unop_log2:
- emit_math(FS_OPCODE_LOG2, this->result, op[0]);
+ emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
break;
case ir_unop_exp:
case ir_unop_log:
@@ -265,11 +265,11 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_unop_sin:
case ir_unop_sin_reduced:
- emit_math(FS_OPCODE_SIN, this->result, op[0]);
+ emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
break;
case ir_unop_cos:
case ir_unop_cos_reduced:
- emit_math(FS_OPCODE_COS, this->result, op[0]);
+ emit_math(SHADER_OPCODE_COS, this->result, op[0]);
break;
case ir_unop_dFdx:
@@ -340,11 +340,11 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_unop_sqrt:
- emit_math(FS_OPCODE_SQRT, this->result, op[0]);
+ emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
break;
case ir_unop_rsq:
- emit_math(FS_OPCODE_RSQ, this->result, op[0]);
+ emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
break;
case ir_unop_i2u:
@@ -423,7 +423,7 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_binop_pow:
- emit_math(FS_OPCODE_POW, this->result, op[0], op[1]);
+ emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
break;
case ir_unop_bit_not:
@@ -1694,7 +1694,7 @@ fs_visitor::emit_interpolation_setup_gen4()
interp_reg(FRAG_ATTRIB_WPOS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
- emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
+ emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
this->current_annotation = NULL;
}
@@ -1731,7 +1731,7 @@ fs_visitor::emit_interpolation_setup_gen6()
this->current_annotation = "compute pos.w";
this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
this->wpos_w = fs_reg(this, glsl_type::float_type);
- emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w);
+ emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
this->delta_x = fs_reg(brw_vec8_grf(2, 0));
this->delta_y = fs_reg(brw_vec8_grf(3, 0));
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 15:46:11 +0000