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-rw-r--r--src/mesa/drivers/dri/i965/intel_context.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.h2
-rw-r--r--src/mesa/drivers/dri/i965/intel_screen.c6
3 files changed, 1 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 27f6b9b69ba..f500c083f59 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -635,8 +635,6 @@ intelInitContext(struct intel_context *intel,
intel_fbo_init(intel);
- intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
-
if (!driQueryOptionb(&intel->optionCache, "hiz")) {
intel->has_hiz = false;
/* On gen6, you can only do separate stencil with HIZ. */
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index e2fdd255aeb..5a4209fb3d2 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -257,8 +257,6 @@ struct intel_context
*/
bool is_front_buffer_reading;
- bool use_early_z;
-
int driFd;
__DRIcontext *driContext;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 8d9d2673146..e207300dca3 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -58,10 +58,6 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
DRI_CONF_OPT_END
- DRI_CONF_OPT_BEGIN_B(early_z, "false")
- DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
- DRI_CONF_OPT_END
-
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_S3TC_ENABLE("false")
@@ -82,7 +78,7 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_END
DRI_CONF_END;
-const GLuint __driNConfigOptions = 14;
+const GLuint __driNConfigOptions = 13;
#include "intel_batchbuffer.h"
#include "intel_buffers.h"