diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2729a54e144..d9ea1057123 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1675,6 +1675,10 @@ enum brw_pixel_shader_coverage_mask_mode { # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7) # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7) +#define COMMON_SLICE_CHICKEN3 0x7304 +# define PS_THREAD_PANIC_DISPATCH (3 << 6) +# define PS_THREAD_PANIC_DISPATCH_MASK REG_MASK(3 << 6) + #define HALF_SLICE_CHICKEN7 0xE194 # define TEXEL_OFFSET_FIX_ENABLE (1 << 1) # define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 1) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 50049d325b3..cc21aca4945 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -108,6 +108,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw) */ brw_load_register_imm32(brw, GEN8_L3CNTLREG, GEN8_L3CNTLREG_EDBC_NO_HANG); + + /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. + */ + brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN3, + PS_THREAD_PANIC_DISPATCH_MASK | + PS_THREAD_PANIC_DISPATCH); } if (devinfo->gen == 10 || devinfo->gen == 11) { |