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-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_nir.cpp21
1 files changed, 15 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 98e023a66d9..71156ec5b3b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -417,15 +417,24 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* We set EmitNoIndirectInput for VS */
assert(const_offset);
+ dest = get_nir_dest(instr->dest);
+ dest.writemask = brw_writemask_for_size(instr->num_components);
+
src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
glsl_type::uvec4_type);
- /* Swizzle source based on component layout qualifier */
- src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
-
- dest = get_nir_dest(instr->dest, src.type);
- dest.writemask = brw_writemask_for_size(instr->num_components);
+ src = retype(src, dest.type);
- emit(MOV(dest, src));
+ bool is_64bit = nir_dest_bit_size(instr->dest) == 64;
+ if (is_64bit) {
+ dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
+ src.swizzle = BRW_SWIZZLE_XYZW;
+ shuffle_64bit_data(tmp, src, false);
+ emit(MOV(dest, src_reg(tmp)));
+ } else {
+ /* Swizzle source based on component layout qualifier */
+ src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
+ emit(MOV(dest, src));
+ }
break;
}