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-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h7
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_surface_state.c11
3 files changed, 14 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 1c70db29e38..68e92a8cd14 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -39,6 +39,8 @@
extern "C" {
#endif
+enum intel_msaa_layout;
+
extern const struct brw_tracked_state brw_blend_constant_color;
extern const struct brw_tracked_state brw_cc_vp;
extern const struct brw_tracked_state brw_cc_unit;
@@ -199,8 +201,9 @@ GLuint translate_tex_format(gl_format mesa_format,
/* gen7_wm_surface_state.c */
void gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling);
-void gen7_set_surface_num_multisamples(struct gen7_surface_state *surf,
- unsigned num_samples);
+void gen7_set_surface_msaa(struct gen7_surface_state *surf,
+ unsigned num_samples,
+ enum intel_msaa_layout layout);
void gen7_set_surface_mcs_info(struct brw_context *brw,
struct gen7_surface_state *surf,
uint32_t surf_offset,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f087dbdc66a..cc28d8c8951 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -180,7 +180,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
pitch_bytes *= 2;
surf->ss3.pitch = pitch_bytes - 1;
- gen7_set_surface_num_multisamples(surf, surface->num_samples);
+ gen7_set_surface_msaa(surf, surface->num_samples, surface->msaa_layout);
if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
gen7_set_surface_mcs_info(brw, surf, wm_surf_offset,
surface->mt->mcs_mt, is_render_target);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index f0370268be8..869f9431b9d 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -56,8 +56,8 @@ gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
void
-gen7_set_surface_num_multisamples(struct gen7_surface_state *surf,
- unsigned num_samples)
+gen7_set_surface_msaa(struct gen7_surface_state *surf, unsigned num_samples,
+ enum intel_msaa_layout layout)
{
if (num_samples > 4)
surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_8;
@@ -65,6 +65,11 @@ gen7_set_surface_num_multisamples(struct gen7_surface_state *surf,
surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_4;
else
surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_1;
+
+ surf->ss4.multisampled_surface_storage_format =
+ layout == INTEL_MSAA_LAYOUT_IMS ?
+ GEN7_SURFACE_MSFMT_DEPTH_STENCIL :
+ GEN7_SURFACE_MSFMT_MSS;
}
@@ -490,7 +495,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
gen7_set_surface_tiling(surf, region->tiling);
surf->ss3.pitch = (region->pitch * region->cpp) - 1;
- gen7_set_surface_num_multisamples(surf, irb->mt->num_samples);
+ gen7_set_surface_msaa(surf, irb->mt->num_samples, irb->mt->msaa_layout);
if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],