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-rw-r--r--src/mesa/pipe/i965simple/brw_curbe.c7
-rw-r--r--src/mesa/pipe/i965simple/brw_draw_upload.c6
-rw-r--r--src/mesa/pipe/i965simple/brw_misc_state.c6
-rw-r--r--src/mesa/pipe/i965simple/brw_state_pool.c10
-rw-r--r--src/mesa/pipe/i965simple/brw_tex_layout.c14
5 files changed, 16 insertions, 27 deletions
diff --git a/src/mesa/pipe/i965simple/brw_curbe.c b/src/mesa/pipe/i965simple/brw_curbe.c
index 4d79a7abe22..2733eb4e75c 100644
--- a/src/mesa/pipe/i965simple/brw_curbe.c
+++ b/src/mesa/pipe/i965simple/brw_curbe.c
@@ -255,15 +255,12 @@ static void upload_constant_buffer(struct brw_context *brw)
/* FIXME: buffer size is num_consts + num_immediates */
if (brw->vs.prog_data->num_consts) {
/* map the vertex constant buffer and copy to curbe: */
- ws->buffer_map(ws, cbuffer->buffer, 0);
+ void *data = ws->buffer_map(ws, cbuffer->buffer, 0);
/* FIXME: this is wrong. the cbuffer->size currently
* represents size of consts + immediates. so if we'll
* have both we'll copy over the end of the buffer
* with the subsequent memcpy */
- ws->buffer_get_subdata(ws, cbuffer->buffer,
- 0,
- cbuffer->size,
- &buf[offset]);
+ memcpy(&buf[offset], data, cbuffer->size);
ws->buffer_unmap(ws, cbuffer->buffer);
offset += cbuffer->size;
}
diff --git a/src/mesa/pipe/i965simple/brw_draw_upload.c b/src/mesa/pipe/i965simple/brw_draw_upload.c
index 88d6c9d1114..43e53914e9d 100644
--- a/src/mesa/pipe/i965simple/brw_draw_upload.c
+++ b/src/mesa/pipe/i965simple/brw_draw_upload.c
@@ -240,7 +240,7 @@ boolean brw_upload_vertex_buffers( struct brw_context *brw )
for (i = 0; i < nr_enabled; i++) {
OUT_BATCH( vbp.vb[i].vb0.dword );
- OUT_RELOC( vbp.vb[i].buffer, PIPE_BUFFER_FLAG_READ,
+ OUT_RELOC( vbp.vb[i].buffer, PIPE_BUFFER_USAGE_GPU_READ,
vbp.vb[i].offset);
OUT_BATCH( vbp.vb[i].max_index );
OUT_BATCH( vbp.vb[i].instance_data_step_rate );
@@ -290,8 +290,8 @@ boolean brw_upload_indices( struct brw_context *brw,
BEGIN_BATCH(4, 0);
OUT_BATCH( ib.header.dword );
- OUT_RELOC( index_buffer, PIPE_BUFFER_FLAG_READ, start);
- OUT_RELOC( index_buffer, PIPE_BUFFER_FLAG_READ, start + count);
+ OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start);
+ OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start + count);
OUT_BATCH( 0 );
ADVANCE_BATCH();
}
diff --git a/src/mesa/pipe/i965simple/brw_misc_state.c b/src/mesa/pipe/i965simple/brw_misc_state.c
index 3b7f36dd1d4..925049ecc19 100644
--- a/src/mesa/pipe/i965simple/brw_misc_state.c
+++ b/src/mesa/pipe/i965simple/brw_misc_state.c
@@ -245,7 +245,7 @@ static void upload_depthbuffer(struct brw_context *brw)
// (depth_surface->region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(depth_surface->buffer,
- PIPE_BUFFER_FLAG_READ | PIPE_BUFFER_FLAG_WRITE, 0);
+ PIPE_BUFFER_USAGE_GPU_READ | PIPE_BUFFER_USAGE_GPU_WRITE, 0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((depth_surface->pitch - 1) << 6) |
((depth_surface->height - 1) << 19));
@@ -465,10 +465,10 @@ static void upload_state_base_address( struct brw_context *brw )
BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_RELOC(brw->pool[BRW_GS_POOL].buffer,
- PIPE_BUFFER_FLAG_READ,
+ PIPE_BUFFER_USAGE_GPU_READ,
1); /* General state base address */
OUT_RELOC(brw->pool[BRW_SS_POOL].buffer,
- PIPE_BUFFER_FLAG_READ,
+ PIPE_BUFFER_USAGE_GPU_READ,
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
diff --git a/src/mesa/pipe/i965simple/brw_state_pool.c b/src/mesa/pipe/i965simple/brw_state_pool.c
index 78268ed8f2e..2f930be837b 100644
--- a/src/mesa/pipe/i965simple/brw_state_pool.c
+++ b/src/mesa/pipe/i965simple/brw_state_pool.c
@@ -91,13 +91,9 @@ static void brw_init_pool( struct brw_context *brw,
pool->brw = brw;
pool->buffer = brw->pipe.winsys->buffer_create(brw->pipe.winsys,
- 4096, 0, 0);
-
- brw->pipe.winsys->buffer_data(brw->pipe.winsys,
- pool->buffer,
- size,
- NULL,
- 0 /* DRM_BO_FLAG_MEM_TT */);
+ 4096,
+ 0 /* DRM_BO_FLAG_MEM_TT */,
+ size);
}
static void brw_destroy_pool( struct brw_context *brw,
diff --git a/src/mesa/pipe/i965simple/brw_tex_layout.c b/src/mesa/pipe/i965simple/brw_tex_layout.c
index 2b2bf16f1be..eadacbf09e8 100644
--- a/src/mesa/pipe/i965simple/brw_tex_layout.c
+++ b/src/mesa/pipe/i965simple/brw_tex_layout.c
@@ -308,15 +308,11 @@ brw_texture_create(struct pipe_context *pipe, struct pipe_texture **pt)
memset(&tex->base + 1, 0,
sizeof(struct brw_texture) - sizeof(struct pipe_texture));
- if (brw_miptree_layout(pipe, tex)) {
- tex->buffer = pipe->winsys->buffer_create(pipe->winsys, 64, 0, 0);
-
- if (tex->buffer)
- pipe->winsys->buffer_data(pipe->winsys, tex->buffer,
- tex->pitch * tex->base.cpp *
- tex->total_height, NULL,
- PIPE_BUFFER_USAGE_PIXEL);
- }
+ if (brw_miptree_layout(pipe, tex))
+ tex->buffer = pipe->winsys->buffer_create(pipe->winsys, 64,
+ PIPE_BUFFER_USAGE_PIXEL,
+ tex->pitch * tex->base.cpp *
+ tex->total_height);
if (!tex->buffer) {
FREE(tex);