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-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c64
-rw-r--r--src/mesa/drivers/dri/i915/i915_state.c2
-rw-r--r--src/mesa/drivers/dri/i915/intel_tris.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp24
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_fp.cpp10
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_constval.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_iz.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen6_sf_state.c16
-rw-r--r--src/mesa/drivers/dri/i965/gen6_wm_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_sf_state.c14
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c2
-rw-r--r--src/mesa/drivers/x11/xm_line.c8
17 files changed, 86 insertions, 86 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 23f2f0f9da0..930c2b876bc 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -97,43 +97,43 @@ src_vector(struct i915_fragment_program *p,
break;
case PROGRAM_INPUT:
switch (source->Index) {
- case FRAG_ATTRIB_WPOS:
+ case VARYING_SLOT_POS:
src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
break;
- case FRAG_ATTRIB_COL0:
+ case VARYING_SLOT_COL0:
src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
break;
- case FRAG_ATTRIB_COL1:
+ case VARYING_SLOT_COL1:
src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
src = swizzle(src, X, Y, Z, ONE);
break;
- case FRAG_ATTRIB_FOGC:
+ case VARYING_SLOT_FOGC:
src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
src = swizzle(src, W, ZERO, ZERO, ONE);
break;
- case FRAG_ATTRIB_TEX0:
- case FRAG_ATTRIB_TEX1:
- case FRAG_ATTRIB_TEX2:
- case FRAG_ATTRIB_TEX3:
- case FRAG_ATTRIB_TEX4:
- case FRAG_ATTRIB_TEX5:
- case FRAG_ATTRIB_TEX6:
- case FRAG_ATTRIB_TEX7:
+ case VARYING_SLOT_TEX0:
+ case VARYING_SLOT_TEX1:
+ case VARYING_SLOT_TEX2:
+ case VARYING_SLOT_TEX3:
+ case VARYING_SLOT_TEX4:
+ case VARYING_SLOT_TEX5:
+ case VARYING_SLOT_TEX6:
+ case VARYING_SLOT_TEX7:
src = i915_emit_decl(p, REG_TYPE_T,
- T_TEX0 + (source->Index - FRAG_ATTRIB_TEX0),
+ T_TEX0 + (source->Index - VARYING_SLOT_TEX0),
D0_CHANNEL_ALL);
break;
- case FRAG_ATTRIB_VAR0:
- case FRAG_ATTRIB_VAR0 + 1:
- case FRAG_ATTRIB_VAR0 + 2:
- case FRAG_ATTRIB_VAR0 + 3:
- case FRAG_ATTRIB_VAR0 + 4:
- case FRAG_ATTRIB_VAR0 + 5:
- case FRAG_ATTRIB_VAR0 + 6:
- case FRAG_ATTRIB_VAR0 + 7:
+ case VARYING_SLOT_VAR0:
+ case VARYING_SLOT_VAR0 + 1:
+ case VARYING_SLOT_VAR0 + 2:
+ case VARYING_SLOT_VAR0 + 3:
+ case VARYING_SLOT_VAR0 + 4:
+ case VARYING_SLOT_VAR0 + 5:
+ case VARYING_SLOT_VAR0 + 6:
+ case VARYING_SLOT_VAR0 + 7:
src = i915_emit_decl(p, REG_TYPE_T,
- T_TEX0 + (source->Index - FRAG_ATTRIB_VAR0),
+ T_TEX0 + (source->Index - VARYING_SLOT_VAR0),
D0_CHANNEL_ALL);
break;
@@ -1152,15 +1152,15 @@ check_wpos(struct i915_fragment_program *p)
p->wpos_tex = -1;
for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
- if (inputs & (FRAG_BIT_TEX(i) | FRAG_BIT_VAR(i)))
+ if (inputs & (VARYING_BIT_TEX(i) | VARYING_BIT_VAR(i)))
continue;
- else if (inputs & FRAG_BIT_WPOS) {
+ else if (inputs & VARYING_BIT_POS) {
p->wpos_tex = i;
- inputs &= ~FRAG_BIT_WPOS;
+ inputs &= ~VARYING_BIT_POS;
}
}
- if (inputs & FRAG_BIT_WPOS) {
+ if (inputs & VARYING_BIT_POS) {
i915_program_error(p, "No free texcoord for wpos value");
}
}
@@ -1359,7 +1359,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
intel->coloroffset = 0;
intel->specoffset = 0;
- if (inputsRead & FRAG_BITS_TEX_ANY || p->wpos_tex != -1) {
+ if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16);
}
else {
@@ -1370,22 +1370,22 @@ i915ValidateFragmentProgram(struct i915_context *i915)
if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled)
EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, S4_VFMT_POINT_WIDTH, 4);
- if (inputsRead & FRAG_BIT_COL0) {
+ if (inputsRead & VARYING_BIT_COL0) {
intel->coloroffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
}
- if (inputsRead & FRAG_BIT_COL1) {
+ if (inputsRead & VARYING_BIT_COL1) {
intel->specoffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_4UB_4F_BGRA, S4_VFMT_SPEC_FOG, 4);
}
- if ((inputsRead & FRAG_BIT_FOGC)) {
+ if ((inputsRead & VARYING_BIT_FOGC)) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
}
for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
- if (inputsRead & FRAG_BIT_TEX(i)) {
+ if (inputsRead & VARYING_BIT_TEX(i)) {
int sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
@@ -1393,7 +1393,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, EMIT_SZ(sz), 0, sz * 4);
}
- else if (inputsRead & FRAG_BIT_VAR(i)) {
+ else if (inputsRead & VARYING_BIT_VAR(i)) {
int sz = VB->AttribPtr[_TNL_ATTRIB_GENERIC0 + i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c
index b4557570202..98eac8df089 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -671,7 +671,7 @@ i915_update_sprite_point_enable(struct gl_context *ctx)
/* _NEW_POINT */
if (ctx->Point.CoordReplace[i] && ctx->Point.PointSprite)
coord_replace_bits |= (1 << i);
- if (inputsRead & FRAG_BIT_TEX(i))
+ if (inputsRead & VARYING_BIT_TEX(i))
tex_coord_unit_bits |= (1 << i);
}
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 549af5e07aa..b97fc98d945 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -955,7 +955,7 @@ intelChooseRenderState(struct gl_context * ctx)
struct intel_context *intel = intel_context(ctx);
GLuint flags = ctx->_TriangleCaps;
const struct gl_fragment_program *fprog = ctx->FragmentProgram._Current;
- bool have_wpos = (fprog && (fprog->Base.InputsRead & FRAG_BIT_WPOS));
+ bool have_wpos = (fprog && (fprog->Base.InputsRead & VARYING_BIT_POS));
GLuint index = 0;
if (INTEL_DEBUG & DEBUG_STATE)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 3d6a8f5a602..d0f5fea3d32 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -953,7 +953,7 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
emit(FS_OPCODE_LINTERP, wpos,
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(FRAG_ATTRIB_WPOS, 2));
+ interp_reg(VARYING_SLOT_POS, 2));
}
wpos.reg_offset++;
@@ -1042,8 +1042,8 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
* attribute, as well as making brw_vs_constval.c
* handle varyings other than gl_TexCoord.
*/
- if (location >= FRAG_ATTRIB_TEX0 &&
- location <= FRAG_ATTRIB_TEX7 &&
+ if (location >= VARYING_SLOT_TEX0 &&
+ location <= VARYING_SLOT_TEX7 &&
k == 3 && !(c->key.proj_attrib_mask
& BITFIELD64_BIT(location))) {
emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
@@ -1245,14 +1245,14 @@ fs_visitor::assign_curb_setup()
void
fs_visitor::calculate_urb_setup()
{
- for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
+ for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
urb_setup[i] = -1;
}
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
if (intel->gen >= 6) {
- for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
+ for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
urb_setup[i] = urb_next++;
}
@@ -1283,8 +1283,8 @@ fs_visitor::calculate_urb_setup()
*
* See compile_sf_prog() for more info.
*/
- if (fp->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
- urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
+ if (fp->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
+ urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
/* Each attribute is 4 setup channels, each of which is half a reg. */
@@ -2690,7 +2690,7 @@ fs_visitor::setup_payload_gen6()
{
struct intel_context *intel = &brw->intel;
bool uses_depth =
- (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
+ (fp->Base.InputsRead & (1 << VARYING_SLOT_POS)) != 0;
unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
assert(intel->gen >= 6);
@@ -2989,9 +2989,9 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
key.proj_attrib_mask = ~(GLbitfield64) 0;
if (intel->gen < 6)
- key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
+ key.vp_outputs_written |= BITFIELD64_BIT(VARYING_SLOT_POS);
- for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
+ for (int i = 0; i < VARYING_SLOT_MAX; i++) {
if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
continue;
@@ -3017,11 +3017,11 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
}
}
- if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
+ if (fp->Base.InputsRead & VARYING_BIT_POS) {
key.drawable_height = ctx->DrawBuffer->Height;
}
- if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
+ if ((fp->Base.InputsRead & VARYING_BIT_POS) || program_uses_dfdy) {
key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index febd56bfe2e..254a53432c8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -452,7 +452,7 @@ public:
int first_non_payload_grf;
/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
int max_grf;
- int urb_setup[FRAG_ATTRIB_MAX];
+ int urb_setup[VARYING_SLOT_MAX];
fs_reg *fp_temp_regs;
fs_reg *fp_input_regs;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 3c0ba245536..5f92955bc7b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -599,8 +599,8 @@ fs_visitor::setup_fp_regs()
}
}
- fp_input_regs = rzalloc_array(mem_ctx, fs_reg, FRAG_ATTRIB_MAX);
- for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
+ fp_input_regs = rzalloc_array(mem_ctx, fs_reg, VARYING_SLOT_MAX);
+ for (int i = 0; i < VARYING_SLOT_MAX; i++) {
if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
/* Make up a dummy instruction to reuse code for emitting
* interpolation.
@@ -614,18 +614,18 @@ fs_visitor::setup_fp_regs()
i);
switch (i) {
- case FRAG_ATTRIB_WPOS:
+ case VARYING_SLOT_POS:
ir->pixel_center_integer = fp->PixelCenterInteger;
ir->origin_upper_left = fp->OriginUpperLeft;
fp_input_regs[i] = *emit_fragcoord_interpolation(ir);
break;
- case FRAG_ATTRIB_FACE:
+ case VARYING_SLOT_FACE:
fp_input_regs[i] = *emit_frontfacing_interpolation(ir);
break;
default:
fp_input_regs[i] = *emit_general_interpolation(ir);
- if (i == FRAG_ATTRIB_FOGC) {
+ if (i == VARYING_SLOT_FOGC) {
emit(MOV(regoffset(fp_input_regs[i], 1), fs_reg(0.0f)));
emit(MOV(regoffset(fp_input_regs[i], 2), fs_reg(0.0f)));
emit(MOV(regoffset(fp_input_regs[i], 3), fs_reg(1.0f)));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 92bc621a5bd..735a33d856b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2034,7 +2034,7 @@ fs_visitor::emit_interpolation_setup_gen4()
emit(FS_OPCODE_LINTERP, wpos_w,
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(FRAG_ATTRIB_WPOS, 3));
+ interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 1132c9a4c00..fdc6bd741c7 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -181,7 +181,7 @@ brw_upload_sf_prog(struct brw_context *brw)
key.point_sprite_coord_replace |= (1 << i);
}
}
- if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
+ if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
key.do_point_coord = 1;
/*
* Window coordinates in a FBO are inverted, which means point
diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c b/src/mesa/drivers/dri/i965/brw_vs_constval.c
index 782f9d734d8..13e8f70e381 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c
@@ -244,10 +244,10 @@ static void calc_wm_input_sizes( struct brw_context *brw )
if (ctx->Point.PointSprite) {
for (int i = 0; i < 8; i++) {
if (ctx->Point.CoordReplace[i]) {
- t.size_masks[4-1] |= FRAG_BIT_TEX(i);
- t.size_masks[3-1] |= FRAG_BIT_TEX(i);
- t.size_masks[2-1] |= FRAG_BIT_TEX(i);
- t.size_masks[1-1] |= FRAG_BIT_TEX(i);
+ t.size_masks[4-1] |= VARYING_BIT_TEX(i);
+ t.size_masks[3-1] |= VARYING_BIT_TEX(i);
+ t.size_masks[2-1] |= VARYING_BIT_TEX(i);
+ t.size_masks[1-1] |= VARYING_BIT_TEX(i);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index e9ef5c7f9d5..39cbbb756ff 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -55,18 +55,18 @@ brw_compute_barycentric_interp_modes(struct brw_context *brw,
* modes are in use, and set the appropriate bits in
* barycentric_interp_modes.
*/
- for (attr = 0; attr < FRAG_ATTRIB_MAX; ++attr) {
+ for (attr = 0; attr < VARYING_SLOT_MAX; ++attr) {
enum glsl_interp_qualifier interp_qualifier =
fprog->InterpQualifier[attr];
bool is_centroid = fprog->IsCentroid & BITFIELD64_BIT(attr);
- bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
+ bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == VARYING_SLOT_COL1;
/* Ignore unused inputs. */
if (!(fprog->Base.InputsRead & BITFIELD64_BIT(attr)))
continue;
/* Ignore WPOS and FACE, because they don't require interpolation. */
- if (attr == FRAG_ATTRIB_WPOS || attr == FRAG_ATTRIB_FACE)
+ if (attr == VARYING_SLOT_POS || attr == VARYING_SLOT_FACE)
continue;
/* Determine the set (or sets) of barycentric coordinates needed to
@@ -462,11 +462,11 @@ static void brw_wm_populate_key( struct brw_context *brw,
* For DRI2 the origin_x/y will always be (0,0) but we still need the
* drawable height in order to invert the Y axis.
*/
- if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS) {
key->drawable_height = ctx->DrawBuffer->Height;
}
- if ((fp->program.Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
+ if ((fp->program.Base.InputsRead & VARYING_BIT_POS) || program_uses_dfdy) {
key->render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
index 2fd1655267b..f1dc5747b5f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
@@ -126,7 +126,7 @@ void fs_visitor::setup_payload_gen4()
bool kill_stats_promoted_workaround = false;
int lookup = c->key.iz_lookup;
bool uses_depth =
- (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
+ (fp->Base.InputsRead & (1 << VARYING_SLOT_POS)) != 0;
assert(lookup < IZ_BIT_MAX);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ea2dea92a70..342a0366257 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -150,7 +150,7 @@ brw_upload_wm_unit(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
wm->wm5.program_uses_depth = (fp->Base.InputsRead &
- (1 << FRAG_ATTRIB_WPOS)) != 0;
+ (1 << VARYING_SLOT_POS)) != 0;
wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
/* _NEW_BUFFERS
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 74b232f008c..7fe1dca50c5 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -56,7 +56,7 @@ uint32_t
get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
int fs_attr, bool two_side_color, uint32_t *max_source_attr)
{
- if (fs_attr == FRAG_ATTRIB_WPOS) {
+ if (fs_attr == VARYING_SLOT_POS) {
/* This attribute will be overwritten by the fragment shader's
* interpolation code (see emit_interp() in brw_wm_fp.c), so just let it
* reference the first available attribute.
@@ -141,7 +141,7 @@ upload_sf_state(struct brw_context *brw)
int attr = 0, input_index = 0;
int urb_entry_read_offset = 1;
float point_size;
- uint16_t attr_overrides[FRAG_ATTRIB_MAX];
+ uint16_t attr_overrides[VARYING_SLOT_MAX];
uint32_t point_sprite_origin;
dw1 = GEN6_SF_SWIZZLE_ENABLE | num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT;
@@ -281,22 +281,22 @@ upload_sf_state(struct brw_context *brw)
* they source from.
*/
uint32_t max_source_attr = 0;
- for (; attr < FRAG_ATTRIB_MAX; attr++) {
+ for (; attr < VARYING_SLOT_MAX; attr++) {
enum glsl_interp_qualifier interp_qualifier =
brw->fragment_program->InterpQualifier[attr];
- bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
+ bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == VARYING_SLOT_COL1;
if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
continue;
/* _NEW_POINT */
if (ctx->Point.PointSprite &&
- (attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7) &&
- ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
+ (attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7) &&
+ ctx->Point.CoordReplace[attr - VARYING_SLOT_TEX0]) {
dw16 |= (1 << input_index);
}
- if (attr == FRAG_ATTRIB_PNTC)
+ if (attr == VARYING_SLOT_PNTC)
dw16 |= (1 << input_index);
/* flat shading */
@@ -320,7 +320,7 @@ upload_sf_state(struct brw_context *brw)
&max_source_attr);
}
- for (; input_index < FRAG_ATTRIB_MAX; input_index++)
+ for (; input_index < VARYING_SLOT_MAX; input_index++)
attr_overrides[input_index] = 0;
/* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index bd28f97add4..5cc0a61a403 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -171,7 +171,7 @@ upload_wm_state(struct brw_context *brw)
dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS)
dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
dw5 |= GEN6_WM_COMPUTED_DEPTH;
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 9171eff7e7b..86809a1b0a3 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -42,7 +42,7 @@ upload_sbe_state(struct brw_context *brw)
int i;
int attr = 0, input_index = 0;
int urb_entry_read_offset = 1;
- uint16_t attr_overrides[FRAG_ATTRIB_MAX];
+ uint16_t attr_overrides[VARYING_SLOT_MAX];
/* _NEW_BUFFERS */
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
uint32_t point_sprite_origin;
@@ -70,21 +70,21 @@ upload_sbe_state(struct brw_context *brw)
* they source from.
*/
uint32_t max_source_attr = 0;
- for (; attr < FRAG_ATTRIB_MAX; attr++) {
+ for (; attr < VARYING_SLOT_MAX; attr++) {
enum glsl_interp_qualifier interp_qualifier =
brw->fragment_program->InterpQualifier[attr];
- bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
+ bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == VARYING_SLOT_COL1;
if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
continue;
if (ctx->Point.PointSprite &&
- attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7 &&
- ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
+ attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7 &&
+ ctx->Point.CoordReplace[attr - VARYING_SLOT_TEX0]) {
dw10 |= (1 << input_index);
}
- if (attr == FRAG_ATTRIB_PNTC)
+ if (attr == VARYING_SLOT_PNTC)
dw10 |= (1 << input_index);
/* flat shading */
@@ -123,7 +123,7 @@ upload_sbe_state(struct brw_context *brw)
dw1 |= urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
- for (; input_index < FRAG_ATTRIB_MAX; input_index++)
+ for (; input_index < VARYING_SLOT_MAX; input_index++)
attr_overrides[input_index] = 0;
BEGIN_BATCH(14);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index e0c69113ada..b0255513cf4 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -58,7 +58,7 @@ upload_wm_state(struct brw_context *brw)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
writes_depth = true;
diff --git a/src/mesa/drivers/x11/xm_line.c b/src/mesa/drivers/x11/xm_line.c
index dc2687df242..b3f6390e0aa 100644
--- a/src/mesa/drivers/x11/xm_line.c
+++ b/src/mesa/drivers/x11/xm_line.c
@@ -423,10 +423,10 @@ xor_line(struct gl_context *ctx, const SWvertex *vert0, const SWvertex *vert1)
vert1->color[0], vert1->color[1],
vert1->color[2], vert1->color[3],
xmesa->pixelformat);
- int x0 = (GLint) vert0->attrib[FRAG_ATTRIB_WPOS][0];
- int y0 = YFLIP(xrb, (GLint) vert0->attrib[FRAG_ATTRIB_WPOS][1]);
- int x1 = (GLint) vert1->attrib[FRAG_ATTRIB_WPOS][0];
- int y1 = YFLIP(xrb, (GLint) vert1->attrib[FRAG_ATTRIB_WPOS][1]);
+ int x0 = (GLint) vert0->attrib[VARYING_SLOT_POS][0];
+ int y0 = YFLIP(xrb, (GLint) vert0->attrib[VARYING_SLOT_POS][1]);
+ int x1 = (GLint) vert1->attrib[VARYING_SLOT_POS][0];
+ int y1 = YFLIP(xrb, (GLint) vert1->attrib[VARYING_SLOT_POS][1]);
XMesaSetForeground(dpy, gc, pixel);
XMesaSetFunction(dpy, gc, GXxor);
XSetLineAttributes(dpy, gc, (int) ctx->Line.Width,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 22:58:38 +0000