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-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c12
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h10
2 files changed, 12 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 90784c5b195..dae0a91fe4f 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -121,15 +121,6 @@ set_blitter_tiling(struct brw_context *brw,
SET_BLITTER_TILING(brw, false, false); \
ADVANCE_BATCH()
-static int
-blt_pitch(struct intel_mipmap_tree *mt)
-{
- int pitch = mt->surf.row_pitch;
- if (mt->surf.tiling != ISL_TILING_LINEAR)
- pitch /= 4;
- return pitch;
-}
-
bool
intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
{
@@ -403,7 +394,8 @@ emit_miptree_blit(struct brw_context *brw,
* for linear surfaces and DWords for tiled surfaces. So the maximum
* pitch is 32k linear and 128k tiled.
*/
- if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
+ if (intel_miptree_blt_pitch(src_mt) >= 32768 ||
+ intel_miptree_blt_pitch(dst_mt) >= 32768) {
perf_debug("Falling back due to >= 32k/128k pitch\n");
return false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index ef8f51840cc..49baa6c7515 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -716,6 +716,16 @@ intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
struct brw_bo **clear_color_bo,
uint32_t *clear_color_offset);
+
+static inline int
+intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
+{
+ int pitch = mt->surf.row_pitch;
+ if (mt->surf.tiling != ISL_TILING_LINEAR)
+ pitch /= 4;
+ return pitch;
+}
+
#ifdef __cplusplus
}
#endif