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-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c14
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c12
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h18
-rw-r--r--src/mesa/drivers/dri/i965/intel_pixel_bitmap.c3
-rw-r--r--src/mesa/drivers/dri/i965/intel_pixel_read.c3
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_image.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_subimage.c2
8 files changed, 32 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index bf7200bd00e..94a166b4f3c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1395,7 +1395,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb->mt->num_samples <= 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
- intel_miptree_resolve_color(brw, rb->mt, 0, 1, 0, 1, 0);
+ intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
} else {
intel_renderbuffer_downsample(brw, rb);
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index dc68614b4d3..e79e02a0752 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -324,11 +324,8 @@ intel_miptree_blit(struct brw_context *brw,
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
- intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
- intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
- intel_miptree_resolve_color(brw, src_mt, src_level, 1, src_slice, 1, 0);
- intel_miptree_resolve_color(brw, dst_mt, dst_level, 1, dst_slice, 1, 0);
- intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
+ intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
+ intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
if (src_flip)
src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
@@ -383,11 +380,8 @@ intel_miptree_copy(struct brw_context *brw,
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
- intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
- intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
- intel_miptree_resolve_color(brw, src_mt, src_level, 1, src_slice, 1, 0);
- intel_miptree_resolve_color(brw, dst_mt, dst_level, 1, dst_slice, 1, 0);
- intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
+ intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
+ intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
uint32_t src_image_x, src_image_y;
intel_miptree_get_image_offset(src_mt, src_level, src_slice,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 04ac46f789c..800b1626964 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2420,8 +2420,10 @@ intel_miptree_make_shareable(struct brw_context *brw,
*/
assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE || mt->num_samples <= 1);
+ intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+ 0, INTEL_REMAINING_LAYERS, false, false);
+
if (mt->mcs_buf) {
- intel_miptree_all_slices_resolve_color(brw, mt, 0);
mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
@@ -2436,7 +2438,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
if (mt->hiz_buf) {
mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
- intel_miptree_all_slices_resolve_depth(brw, mt);
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
@@ -3194,11 +3195,8 @@ intel_miptree_map(struct brw_context *brw,
return;
}
- intel_miptree_resolve_color(brw, mt, level, 1, slice, 1, 0);
- intel_miptree_slice_resolve_depth(brw, mt, level, slice);
- if (map->mode & GL_MAP_WRITE_BIT) {
- intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice);
- }
+ intel_miptree_access_raw(brw, mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_map_s8(brw, mt, map, level, slice);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 77572292f63..a3d68e62f37 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -1027,6 +1027,24 @@ intel_miptree_set_aux_state(struct brw_context *brw,
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_state aux_state);
+/**
+ * Prepare a miptree for raw access
+ *
+ * This helper prepares the miptree for access that knows nothing about any
+ * sort of compression whatsoever. This is useful when mapping the surface or
+ * using it with the blitter.
+ */
+static inline void
+intel_miptree_access_raw(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t level, uint32_t layer,
+ bool write)
+{
+ intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
+ if (write)
+ intel_miptree_finish_write(brw, mt, level, layer, 1, false);
+}
+
void
intel_miptree_make_shareable(struct brw_context *brw,
struct intel_mipmap_tree *mt);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index f79863e3493..af94a1c82f5 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -256,8 +256,7 @@ do_blit_bitmap( struct gl_context *ctx,
/* The blitter has no idea about fast color clears, so we need to resolve
* the miptree before we do anything.
*/
- intel_miptree_resolve_color(brw, irb->mt, irb->mt_level, 1,
- irb->mt_layer, 1, 0);
+ intel_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, true);
/* Chop it all into chunks that can be digested by hardware: */
for (py = 0; py < height; py += DY) {
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 7892b37a077..871559edf9e 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -147,8 +147,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
/* Since we are going to read raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
- intel_miptree_resolve_color(brw, irb->mt, irb->mt_level, 1,
- irb->mt_layer, 1, 0);
+ intel_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, false);
bo = irb->mt->bo;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 8cd1eae296b..ea166f019fb 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -539,7 +539,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
* any pending fast color clears before we start.
*/
assert(image->mt->logical_depth0 == 1);
- intel_miptree_resolve_color(brw, image->mt, level, 1, 0, 1, 0);
+ intel_miptree_access_raw(brw, image->mt, level, 0, true);
bo = image->mt->bo;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index caa673001fd..da5b3f0d302 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -151,7 +151,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
* any pending fast color clears before we start.
*/
assert(image->mt->logical_depth0 == 1);
- intel_miptree_resolve_color(brw, image->mt, level, 1, 0, 1, 0);
+ intel_miptree_access_raw(brw, image->mt, level, 0, true);
bo = image->mt->bo;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 02:13:19 +0000