diff options
Diffstat (limited to 'src/mesa/drivers')
45 files changed, 299 insertions, 228 deletions
diff --git a/src/mesa/drivers/common/driverfuncs.c b/src/mesa/drivers/common/driverfuncs.c index 5389a500111..854dea94504 100644 --- a/src/mesa/drivers/common/driverfuncs.c +++ b/src/mesa/drivers/common/driverfuncs.c @@ -42,6 +42,7 @@ #include "main/fbobject.h" #include "main/texrender.h" #include "main/syncobj.h" +#include "main/texturebarrier.h" #include "main/transformfeedback.h" #include "program/program.h" @@ -188,6 +189,8 @@ _mesa_init_driver_functions(struct dd_function_table *driver) driver->BlitFramebuffer = _swrast_BlitFramebuffer; + _mesa_init_texture_barrier_functions(driver); + /* APPLE_vertex_array_object */ driver->NewArrayObject = _mesa_new_array_object; driver->DeleteArrayObject = _mesa_delete_array_object; diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c index 42be77fd7c4..083edfaa9b4 100644 --- a/src/mesa/drivers/dri/common/utils.c +++ b/src/mesa/drivers/dri/common/utils.c @@ -648,6 +648,8 @@ driCreateConfigs(GLenum fb_format, GLenum fb_type, __DRI_ATTRIB_TEXTURE_1D_BIT | __DRI_ATTRIB_TEXTURE_2D_BIT | __DRI_ATTRIB_TEXTURE_RECTANGLE_BIT; + + modes->sRGBCapable = GL_FALSE; } } } @@ -727,6 +729,7 @@ static const struct { unsigned int attrib, offset; } attribMap[] = { __ATTRIB(__DRI_ATTRIB_BIND_TO_MIPMAP_TEXTURE, bindToMipmapTexture), __ATTRIB(__DRI_ATTRIB_BIND_TO_TEXTURE_TARGETS, bindToTextureTargets), __ATTRIB(__DRI_ATTRIB_YINVERTED, yInverted), + __ATTRIB(__DRI_ATTRIB_FRAMEBUFFER_SRGB_CAPABLE, sRGBCapable), /* The struct field doesn't matter here, these are handled by the * switch in driGetConfigAttribIndex. We need them in the array diff --git a/src/mesa/drivers/dri/i915/i830_state.c b/src/mesa/drivers/dri/i915/i830_state.c index ef5b8d971da..9fecab10db9 100644 --- a/src/mesa/drivers/dri/i915/i830_state.c +++ b/src/mesa/drivers/dri/i915/i830_state.c @@ -31,6 +31,7 @@ #include "main/macros.h" #include "main/enums.h" #include "main/dd.h" +#include "main/state.h" #include "texmem.h" @@ -234,7 +235,7 @@ i830EvalLogicOpBlendState(struct gl_context * ctx) I830_STATECHANGE(i830, I830_UPLOAD_CTX); - if (RGBA_LOGICOP_ENABLED(ctx)) { + if (_mesa_rgba_logicop_enabled(ctx)) { i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND | ENABLE_LOGIC_OP_MASK); i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (DISABLE_COLOR_BLEND | @@ -679,7 +680,7 @@ update_specular(struct gl_context * ctx) I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_SPEC_ADD_MASK; - if (NEED_SECONDARY_COLOR(ctx)) + if (_mesa_need_secondary_color(ctx)) i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_SPEC_ADD; else i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_SPEC_ADD; diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c index 25f4fc3c8b1..2bfe665cb65 100644 --- a/src/mesa/drivers/dri/i915/i915_fragprog.c +++ b/src/mesa/drivers/dri/i915/i915_fragprog.c @@ -269,7 +269,7 @@ translate_tex_src_target(struct i915_fragment_program *p, GLubyte bit) #define EMIT_TEX( OP ) \ do { \ GLuint dim = translate_tex_src_target( p, inst->TexSrcTarget ); \ - const struct gl_fragment_program *program = p->ctx->FragmentProgram._Current; \ + const struct gl_fragment_program *program = &p->FragProg; \ GLuint unit = program->Base.SamplerUnits[inst->TexSrcUnit]; \ GLuint sampler = i915_emit_decl(p, REG_TYPE_S, \ unit, dim); \ @@ -304,7 +304,7 @@ do { \ */ static void calc_live_regs( struct i915_fragment_program *p ) { - const struct gl_fragment_program *program = p->ctx->FragmentProgram._Current; + const struct gl_fragment_program *program = &p->FragProg; GLuint regsUsed = 0xffff0000; uint8_t live_components[16] = { 0, }; GLint i; @@ -344,7 +344,7 @@ static void calc_live_regs( struct i915_fragment_program *p ) static GLuint get_live_regs( struct i915_fragment_program *p, const struct prog_instruction *inst ) { - const struct gl_fragment_program *program = p->ctx->FragmentProgram._Current; + const struct gl_fragment_program *program = &p->FragProg; GLuint nr = inst - program->Base.Instructions; return p->usedRegs[nr]; @@ -365,8 +365,7 @@ static GLuint get_live_regs( struct i915_fragment_program *p, static void upload_program(struct i915_fragment_program *p) { - const struct gl_fragment_program *program = - p->ctx->FragmentProgram._Current; + const struct gl_fragment_program *program = &p->FragProg; const struct prog_instruction *inst = program->Base.Instructions; if (INTEL_DEBUG & DEBUG_WM) @@ -1166,7 +1165,7 @@ translate_program(struct i915_fragment_program *p) if (INTEL_DEBUG & DEBUG_WM) { printf("fp:\n"); - _mesa_print_program(&p->ctx->FragmentProgram._Current->Base); + _mesa_print_program(&p->FragProg.Base); printf("\n"); } diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c index 58d4f5daffd..3b1af4c455e 100644 --- a/src/mesa/drivers/dri/i915/i915_state.c +++ b/src/mesa/drivers/dri/i915/i915_state.c @@ -31,6 +31,7 @@ #include "main/macros.h" #include "main/enums.h" #include "main/dd.h" +#include "main/state.h" #include "tnl/tnl.h" #include "tnl/t_context.h" @@ -209,7 +210,7 @@ i915EvalLogicOpBlendState(struct gl_context * ctx) dw0 = i915->state.Ctx[I915_CTXREG_LIS5]; dw1 = i915->state.Ctx[I915_CTXREG_LIS6]; - if (RGBA_LOGICOP_ENABLED(ctx)) { + if (_mesa_rgba_logicop_enabled(ctx)) { dw0 |= S5_LOGICOP_ENABLE; dw1 &= ~S6_CBUF_BLEND_ENABLE; } diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index cf9291cdfca..7bcb72f42d0 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -490,6 +490,7 @@ static void intel_wpos_triangle(struct intel_context *intel, intelVertexPtr v0, intelVertexPtr v1, intelVertexPtr v2) { + const struct gl_framebuffer *fb = intel->ctx.DrawBuffer; GLuint offset = intel->wpos_offset; GLuint size = intel->wpos_size; GLfloat *v0_wpos = (GLfloat *)((char *)v0 + offset); @@ -500,10 +501,11 @@ intel_wpos_triangle(struct intel_context *intel, __memcpy(v1_wpos, v1, size); __memcpy(v2_wpos, v2, size); - v0_wpos[1] = -v0_wpos[1] + intel->ctx.DrawBuffer->Height; - v1_wpos[1] = -v1_wpos[1] + intel->ctx.DrawBuffer->Height; - v2_wpos[1] = -v2_wpos[1] + intel->ctx.DrawBuffer->Height; - + if (!fb->Name) { + v0_wpos[1] = -v0_wpos[1] + fb->Height; + v1_wpos[1] = -v1_wpos[1] + fb->Height; + v2_wpos[1] = -v2_wpos[1] + fb->Height; + } intel_draw_triangle(intel, v0, v1, v2); } @@ -513,6 +515,7 @@ static void intel_wpos_line(struct intel_context *intel, intelVertexPtr v0, intelVertexPtr v1) { + const struct gl_framebuffer *fb = intel->ctx.DrawBuffer; GLuint offset = intel->wpos_offset; GLuint size = intel->wpos_size; GLfloat *v0_wpos = (GLfloat *)((char *)v0 + offset); @@ -521,8 +524,10 @@ intel_wpos_line(struct intel_context *intel, __memcpy(v0_wpos, v0, size); __memcpy(v1_wpos, v1, size); - v0_wpos[1] = -v0_wpos[1] + intel->ctx.DrawBuffer->Height; - v1_wpos[1] = -v1_wpos[1] + intel->ctx.DrawBuffer->Height; + if (!fb->Name) { + v0_wpos[1] = -v0_wpos[1] + fb->Height; + v1_wpos[1] = -v1_wpos[1] + fb->Height; + } intel_draw_line(intel, v0, v1); } @@ -531,12 +536,15 @@ intel_wpos_line(struct intel_context *intel, static void intel_wpos_point(struct intel_context *intel, intelVertexPtr v0) { + const struct gl_framebuffer *fb = intel->ctx.DrawBuffer; GLuint offset = intel->wpos_offset; GLuint size = intel->wpos_size; GLfloat *v0_wpos = (GLfloat *)((char *)v0 + offset); __memcpy(v0_wpos, v0, size); - v0_wpos[1] = -v0_wpos[1] + intel->ctx.DrawBuffer->Height; + + if (!fb->Name) + v0_wpos[1] = -v0_wpos[1] + fb->Height; intel_draw_point(intel, v0); } diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 26a6388f342..7b0551a92bc 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -701,6 +701,9 @@ struct brw_context /* Used to give every program string a unique id */ GLuint program_id; + + int num_prepare_atoms, num_emit_atoms; + struct brw_tracked_state prepare_atoms[64], emit_atoms[64]; }; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 5496b4fdd3b..6c61aefd7d3 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -688,13 +688,13 @@ #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 -#define BRW_SAMPLER_MESSAGE_SAMPLE_GEN5 0 -#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5 1 -#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5 2 -#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5 3 -#define BRW_SAMPLER_MESSAGE_SAMPLE_DERIVS_GEN5 4 -#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5 5 -#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE_GEN5 6 +#define GEN5_SAMPLER_MESSAGE_SAMPLE 0 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 +#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 /* for GEN5 only */ #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 @@ -752,14 +752,14 @@ #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 /* GEN6 */ -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE_GEN6 7 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE_GEN6 8 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE_GEN6 9 -#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE_GEN6 10 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE_GEN6 11 -#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6 12 -#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE_GEN6 13 -#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE_GEN6 14 +#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 +#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 +#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 +#define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 +#define GEN6_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE 11 +#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 +#define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 +#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 #define BRW_MATH_FUNCTION_INV 1 #define BRW_MATH_FUNCTION_LOG 2 diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index e96c32a93a6..f1d00693168 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -291,7 +291,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Accumulate the list of enabled arrays. */ brw->vb.nr_enabled = 0; while (vs_inputs) { - GLuint i = _mesa_ffsll(vs_inputs) - 1; + GLuint i = ffs(vs_inputs) - 1; struct brw_vertex_element *input = &brw->vb.inputs[i]; vs_inputs &= ~(1 << i); diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 119ffc72370..2d2ed9de985 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -939,8 +939,8 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p, */ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size); -struct brw_instruction *brw_IF_gen6(struct brw_compile *p, uint32_t conditional, - struct brw_reg src0, struct brw_reg src1); +struct brw_instruction *gen6_IF(struct brw_compile *p, uint32_t conditional, + struct brw_reg src0, struct brw_reg src1); struct brw_instruction *brw_ELSE(struct brw_compile *p, struct brw_instruction *if_insn); @@ -958,9 +958,9 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *patch_insn); struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count); -struct brw_instruction *brw_CONT_gen6(struct brw_compile *p, - struct brw_instruction *do_insn); struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count); +struct brw_instruction *gen6_CONT(struct brw_compile *p, + struct brw_instruction *do_insn); /* Forward jumps: */ void brw_land_fwd_jump(struct brw_compile *p, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 88131c432ec..21ce92c9173 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -874,8 +874,8 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) } struct brw_instruction * -brw_IF_gen6(struct brw_compile *p, uint32_t conditional, - struct brw_reg src0, struct brw_reg src1) +gen6_IF(struct brw_compile *p, uint32_t conditional, + struct brw_reg src0, struct brw_reg src1) { struct brw_instruction *insn; @@ -1061,8 +1061,8 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count) return insn; } -struct brw_instruction *brw_CONT_gen6(struct brw_compile *p, - struct brw_instruction *do_insn) +struct brw_instruction *gen6_CONT(struct brw_compile *p, + struct brw_instruction *do_insn) { struct brw_instruction *insn; int br = 2; @@ -1844,7 +1844,7 @@ void brw_fb_WRITE(struct brw_compile *p, /* headerless version, just submit color payload */ src0 = brw_message_reg(msg_reg_nr); - msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6; + msg_type = GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; } else { insn->header.destreg__conditionalmod = msg_reg_nr; diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index ce7959b19de..8b3f5adb9f9 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -78,15 +78,6 @@ brw_new_shader_program(struct gl_context *ctx, GLuint name) } GLboolean -brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader) -{ - if (!_mesa_ir_compile_shader(ctx, shader)) - return GL_FALSE; - - return GL_TRUE; -} - -GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) { struct brw_context *brw = brw_context(ctx); @@ -120,6 +111,14 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) do_lower_texture_projection(shader->ir); do_vec_index_to_cond_assign(shader->ir); brw_do_cubemap_normalize(shader->ir); + lower_noise(shader->ir); + lower_quadop_vector(shader->ir, false); + lower_variable_index_to_cond_assign(shader->ir, + GL_TRUE, /* input */ + GL_TRUE, /* output */ + GL_TRUE, /* temp */ + GL_TRUE /* uniform */ + ); do { progress = false; @@ -134,16 +133,6 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) ) || progress; progress = do_common_optimization(shader->ir, true, 32) || progress; - - progress = lower_noise(shader->ir) || progress; - progress = - lower_variable_index_to_cond_assign(shader->ir, - GL_TRUE, /* input */ - GL_TRUE, /* output */ - GL_TRUE, /* temp */ - GL_TRUE /* uniform */ - ) || progress; - progress = lower_quadop_vector(shader->ir, false) || progress; } while (progress); validate_ir_tree(shader->ir); @@ -1452,7 +1441,10 @@ fs_visitor::visit(ir_texture *ir) if (ir->shadow_comparitor) inst->shadow_compare = true; - if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { + if (ir->type == glsl_type::float_type) { + /* Ignore DEPTH_TEXTURE_MODE swizzling. */ + assert(ir->sampler->type->sampler_shadow); + } else if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type); for (int i = 0; i < 4; i++) { @@ -2139,6 +2131,17 @@ fs_visitor::emit_fb_writes() } if (c->key.nr_color_regions == 0) { + if (c->key.alpha_test && (this->frag_color || this->frag_data)) { + /* If the alpha test is enabled but there's no color buffer, + * we still need to send alpha out the pipeline to our null + * renderbuffer. + */ + color.reg_offset += 3; + emit(fs_inst(BRW_OPCODE_MOV, + fs_reg(MRF, color_mrf + 3), + color)); + } + fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE, reg_undef, reg_undef)); inst->base_mrf = 0; @@ -2301,23 +2304,23 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) switch (inst->opcode) { case FS_OPCODE_TEX: if (inst->shadow_compare) { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; } else { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; } break; case FS_OPCODE_TXB: if (inst->shadow_compare) { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; } else { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; } break; case FS_OPCODE_TXL: if (inst->shadow_compare) { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; } else { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; } break; case FS_OPCODE_TXD: @@ -3542,7 +3545,7 @@ fs_visitor::generate_code() case BRW_OPCODE_IF: if (inst->src[0].file != BAD_FILE) { assert(intel->gen >= 6); - if_stack[if_stack_depth] = brw_IF_gen6(p, inst->conditional_mod, src[0], src[1]); + if_stack[if_stack_depth] = gen6_IF(p, inst->conditional_mod, src[0], src[1]); } else { if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8); } @@ -3584,7 +3587,7 @@ fs_visitor::generate_code() case BRW_OPCODE_CONTINUE: /* FINISHME: We need to write the loop instruction support still. */ if (intel->gen >= 6) - brw_CONT_gen6(p, loop_stack[loop_stack_depth - 1]); + gen6_CONT(p, loop_stack[loop_stack_depth - 1]); else brw_CONT(p, if_depth_in_loop[loop_stack_depth]); brw_set_predicate_control(p, BRW_PREDICATE_NONE); diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 7d653327e30..ee68095fceb 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -243,7 +243,6 @@ void brwInitFragProgFuncs( struct dd_function_table *functions ) functions->NewShader = brw_new_shader; functions->NewShaderProgram = brw_new_shader_program; - functions->CompileShader = brw_compile_shader; functions->LinkShader = brw_link_shader; } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 2d6fb37355d..6f521be6599 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -104,7 +104,7 @@ static const struct brw_tracked_state *gen4_atoms[] = &brw_constant_buffer }; -const struct brw_tracked_state *gen6_atoms[] = +static const struct brw_tracked_state *gen6_atoms[] = { &brw_check_fallback, @@ -169,7 +169,32 @@ const struct brw_tracked_state *gen6_atoms[] = void brw_init_state( struct brw_context *brw ) { + const struct brw_tracked_state **atoms; + int num_atoms; + brw_init_caches(brw); + + if (brw->intel.gen >= 6) { + atoms = gen6_atoms; + num_atoms = ARRAY_SIZE(gen6_atoms); + } else { + atoms = gen4_atoms; + num_atoms = ARRAY_SIZE(gen4_atoms); + } + + while (num_atoms--) { + assert((*atoms)->dirty.mesa | + (*atoms)->dirty.brw | + (*atoms)->dirty.cache); + + if ((*atoms)->prepare) + brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms; + if ((*atoms)->emit) + brw->emit_atoms[brw->num_emit_atoms++] = **atoms; + atoms++; + } + assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms)); + assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms)); } @@ -186,7 +211,7 @@ static GLuint check_state( const struct brw_state_flags *a, { return ((a->mesa & b->mesa) | (a->brw & b->brw) | - (a->cache & b->cache)); + (a->cache & b->cache)) != 0; } static void accumulate_state( struct brw_state_flags *a, @@ -342,9 +367,9 @@ void brw_validate_state( struct brw_context *brw ) struct gl_context *ctx = &brw->intel.ctx; struct intel_context *intel = &brw->intel; struct brw_state_flags *state = &brw->state.dirty; + const struct brw_tracked_state *atoms = brw->prepare_atoms; + int num_atoms = brw->num_prepare_atoms; GLuint i; - const struct brw_tracked_state **atoms; - int num_atoms; brw_clear_validated_bos(brw); @@ -353,14 +378,6 @@ void brw_validate_state( struct brw_context *brw ) brw_add_validated_bo(brw, intel->batch.bo); - if (intel->gen >= 6) { - atoms = gen6_atoms; - num_atoms = ARRAY_SIZE(gen6_atoms); - } else { - atoms = gen4_atoms; - num_atoms = ARRAY_SIZE(gen4_atoms); - } - if (brw->emit_state_always) { state->mesa |= ~0; state->brw |= ~0; @@ -384,15 +401,13 @@ void brw_validate_state( struct brw_context *brw ) /* do prepare stage for all atoms */ for (i = 0; i < num_atoms; i++) { - const struct brw_tracked_state *atom = atoms[i]; - - if (brw->intel.Fallback) - break; + const struct brw_tracked_state *atom = &atoms[i]; if (check_state(state, &atom->dirty)) { - if (atom->prepare) { - atom->prepare(brw); - } + atom->prepare(brw); + + if (brw->intel.Fallback) + break; } } @@ -415,20 +430,11 @@ void brw_validate_state( struct brw_context *brw ) void brw_upload_state(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; struct brw_state_flags *state = &brw->state.dirty; + const struct brw_tracked_state *atoms = brw->emit_atoms; + int num_atoms = brw->num_emit_atoms; int i; static int dirty_count = 0; - const struct brw_tracked_state **atoms; - int num_atoms; - - if (intel->gen >= 6) { - atoms = gen6_atoms; - num_atoms = ARRAY_SIZE(gen6_atoms); - } else { - atoms = gen4_atoms; - num_atoms = ARRAY_SIZE(gen4_atoms); - } brw_clear_validated_bos(brw); @@ -442,20 +448,14 @@ void brw_upload_state(struct brw_context *brw) prev = *state; for (i = 0; i < num_atoms; i++) { - const struct brw_tracked_state *atom = atoms[i]; + const struct brw_tracked_state *atom = &atoms[i]; struct brw_state_flags generated; - assert(atom->dirty.mesa || - atom->dirty.brw || - atom->dirty.cache); - if (brw->intel.Fallback) break; if (check_state(state, &atom->dirty)) { - if (atom->emit) { - atom->emit( brw ); - } + atom->emit(brw); } accumulate_state(&examined, &atom->dirty); @@ -471,15 +471,13 @@ void brw_upload_state(struct brw_context *brw) } else { for (i = 0; i < num_atoms; i++) { - const struct brw_tracked_state *atom = atoms[i]; + const struct brw_tracked_state *atom = &atoms[i]; if (brw->intel.Fallback) break; if (check_state(state, &atom->dirty)) { - if (atom->emit) { - atom->emit( brw ); - } + atom->emit(brw); } } } diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 6ec62554cc4..acacf374b75 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -2109,7 +2109,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) case OPCODE_CONT: brw_set_predicate_control(p, get_predicate(inst)); if (intel->gen >= 6) { - brw_CONT_gen6(p, loop_inst[loop_depth - 1]); + gen6_CONT(p, loop_inst[loop_depth - 1]); } else { brw_CONT(p, if_depth_in_loop[loop_depth]); } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index ee8212f6f16..ca51d1599a4 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -284,6 +284,7 @@ static void brw_wm_populate_key( struct brw_context *brw, /* Build the index for table lookup */ /* _NEW_COLOR */ + key->alpha_test = ctx->Color.AlphaEnabled; if (fp->program.UsesKill || ctx->Color.AlphaEnabled) lookup |= IZ_PS_KILL_ALPHATEST_BIT; @@ -364,8 +365,6 @@ static void brw_wm_populate_key( struct brw_context *brw, SWIZZLE_NIL }; - key->tex_swizzles[i] = SWIZZLE_NOOP; - /* GL_DEPTH_TEXTURE_MODE is normally handled through * brw_wm_surface_state, but it applies to shadow compares as * well and our shadow compares always return the result in @@ -379,9 +378,10 @@ static void brw_wm_populate_key( struct brw_context *brw, } else if (t->DepthMode == GL_LUMINANCE) { swizzles[3] = SWIZZLE_ONE; } else if (t->DepthMode == GL_RED) { + /* See table 3.23 of the GL 3.0 spec. */ swizzles[1] = SWIZZLE_ZERO; swizzles[2] = SWIZZLE_ZERO; - swizzles[3] = SWIZZLE_ZERO; + swizzles[3] = SWIZZLE_ONE; } } diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index d9cae75ab5b..c40d7bfae0a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -64,6 +64,7 @@ struct brw_wm_prog_key { GLuint linear_color:1; /**< linear interpolation vs perspective interp */ GLuint nr_color_regions:5; GLuint render_to_fbo:1; + GLuint alpha_test:1; GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */ GLuint shadowtex_mask:16; @@ -467,8 +468,6 @@ void emit_xpd(struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1); -GLboolean brw_compile_shader(struct gl_context *ctx, - struct gl_shader *shader); GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog); struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type); struct gl_shader_program *brw_new_shader_program(struct gl_context *ctx, GLuint name); diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 2336e27c1ef..ecfd21d4399 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1134,9 +1134,9 @@ void emit_tex(struct brw_wm_compile *c, if (intel->gen >= 5) { if (shadow) - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; else - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; } else { /* Note that G45 and older determines shadow compare and dispatch width * from message length for most messages. @@ -1186,14 +1186,14 @@ void emit_txb(struct brw_wm_compile *c, */ if (c->dispatch_width == 16 || intel->gen < 5) { if (intel->gen >= 5) - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; else msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; mrf_per_channel = 2; dst_retyped = retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW); response_length = 8; } else { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; mrf_per_channel = 1; dst_retyped = retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW); response_length = 4; diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index d398775906e..43cdd0d2bac 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -208,7 +208,7 @@ do_blit_bitmap( struct gl_context *ctx, COPY_4V(tmpColor, ctx->Current.RasterColor); - if (NEED_SECONDARY_COLOR(ctx)) { + if (_mesa_need_secondary_color(ctx)) { ADD_3V(tmpColor, tmpColor, ctx->Current.RasterSecondaryColor); } diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 0857fa8ad70..a4da1ce4fa5 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -149,11 +149,6 @@ intel_region_alloc_internal(struct intel_screen *screen, { struct intel_region *region; - if (buffer == NULL) { - _DBG("%s <-- NULL\n", __FUNCTION__); - return NULL; - } - region = calloc(sizeof(*region), 1); if (region == NULL) return region; @@ -180,6 +175,7 @@ intel_region_alloc(struct intel_screen *screen, drm_intel_bo *buffer; unsigned long flags = 0; unsigned long aligned_pitch; + struct intel_region *region; if (expect_accelerated_upload) flags |= BO_ALLOC_FOR_RENDER; @@ -187,9 +183,17 @@ intel_region_alloc(struct intel_screen *screen, buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region", width, height, cpp, &tiling, &aligned_pitch, flags); + if (buffer == NULL) + return NULL; - return intel_region_alloc_internal(screen, cpp, width, height, - aligned_pitch / cpp, tiling, buffer); + region = intel_region_alloc_internal(screen, cpp, width, height, + aligned_pitch / cpp, tiling, buffer); + if (region == NULL) { + drm_intel_bo_unreference(buffer); + return NULL; + } + + return region; } GLboolean diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 5c95c72732e..64a21a147f0 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -25,6 +25,7 @@ * **************************************************************************/ +#include <errno.h> #include "main/glheader.h" #include "main/context.h" #include "main/framebuffer.h" @@ -302,7 +303,8 @@ intel_get_param(__DRIscreen *psp, int param, int *value) ret = drmCommandWriteRead(psp->fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); if (ret) { - _mesa_warning(NULL, "drm_i915_getparam: %d", ret); + if (ret != -EINVAL) + _mesa_warning(NULL, "drm_i915_getparam: %d", ret); return GL_FALSE; } diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 6b7f13ff353..d0f8294113a 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -90,19 +90,19 @@ intelTexSubimage(struct gl_context * ctx, intel->gen < 6 && target == GL_TEXTURE_2D && drm_intel_bo_busy(dst_bo)) { - unsigned long pitch; - uint32_t tiling_mode = I915_TILING_NONE; - temp_bo = drm_intel_bo_alloc_tiled(intel->bufmgr, - "subimage blit bo", - width, height, - intelImage->mt->cpp, - &tiling_mode, - &pitch, - 0); - drm_intel_gem_bo_map_gtt(temp_bo); + dstRowStride = width * intelImage->mt->cpp; + temp_bo = drm_intel_bo_alloc(intel->bufmgr, "subimage blit bo", + dstRowStride * height, 0); + if (!temp_bo) + return; + + if (drm_intel_gem_bo_map_gtt(temp_bo)) { + drm_intel_bo_unreference(temp_bo); + return; + } + texImage->Data = temp_bo->virtual; texImage->ImageOffsets[0] = 0; - dstRowStride = pitch; intel_miptree_get_image_offset(intelImage->mt, level, intelImage->face, 0, diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 8537e7f3682..a11b07ed09d 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -140,6 +140,8 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) cpp, comp_byte, GL_TRUE); + if (!intelObj->mt) + return GL_FALSE; } /* Pull in any images not in the object's tree: diff --git a/src/mesa/drivers/dri/mga/mgastate.c b/src/mesa/drivers/dri/mga/mgastate.c index 2fac2b49cd2..bfc55f4fc6d 100644 --- a/src/mesa/drivers/dri/mga/mgastate.c +++ b/src/mesa/drivers/dri/mga/mgastate.c @@ -30,6 +30,7 @@ #include "main/colormac.h" #include "main/dd.h" #include "main/mm.h" +#include "main/state.h" #include "mgacontext.h" #include "mgadd.h" @@ -114,7 +115,7 @@ static void mgaDDAlphaFunc(struct gl_context *ctx, GLenum func, GLfloat ref) static void updateBlendLogicOp(struct gl_context *ctx) { mgaContextPtr mmesa = MGA_CONTEXT(ctx); - GLboolean logicOp = RGBA_LOGICOP_ENABLED(ctx); + GLboolean logicOp = _mesa_rgba_logicop_enabled(ctx); MGA_STATECHANGE( mmesa, MGA_UPLOAD_CONTEXT ); @@ -197,7 +198,7 @@ static void mgaDDBlendFuncSeparate( struct gl_context *ctx, GLenum sfactorRGB, mmesa->hw.blend_func = (src | dst); FALLBACK( ctx, MGA_FALLBACK_BLEND, - ctx->Color.BlendEnabled && !RGBA_LOGICOP_ENABLED(ctx) && + ctx->Color.BlendEnabled && !_mesa_rgba_logicop_enabled(ctx) && mmesa->hw.blend_func == (AC_src_src_alpha_sat | AC_dst_zero) ); } @@ -483,7 +484,7 @@ static void updateSpecularLighting( struct gl_context *ctx ) mgaContextPtr mmesa = MGA_CONTEXT(ctx); unsigned int specen; - specen = NEED_SECONDARY_COLOR(ctx) ? TMC_specen_enable : 0; + specen = _mesa_need_secondary_color(ctx) ? TMC_specen_enable : 0; if ( specen != mmesa->hw.specen ) { mmesa->hw.specen = specen; @@ -962,7 +963,7 @@ void mgaEmitHwStateLocked( mgaContextPtr mmesa ) ? mmesa->hw.zmode : (DC_zmode_nozcmp | DC_atype_i); mmesa->setup.dwgctl &= DC_bop_MASK; - mmesa->setup.dwgctl |= RGBA_LOGICOP_ENABLED(ctx) + mmesa->setup.dwgctl |= _mesa_rgba_logicop_enabled(ctx) ? mmesa->hw.rop : mgarop_NoBLK[ GL_COPY & 0x0f ]; mmesa->setup.alphactrl &= AC_src_MASK & AC_dst_MASK & AC_atmode_MASK diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.h b/src/mesa/drivers/dri/nouveau/nouveau_driver.h index c5ac1282d0d..158aec820aa 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_driver.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.h @@ -31,6 +31,7 @@ #include "main/mtypes.h" #include "main/macros.h" #include "main/formats.h" +#include "main/state.h" #include "utils.h" #include "dri_util.h" diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c b/src/mesa/drivers/dri/nouveau/nouveau_texture.c index 988208ff56e..1a1e10e0b3a 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c @@ -30,6 +30,7 @@ #include "nouveau_fbo.h" #include "nouveau_util.h" +#include "main/pbo.h" #include "main/texobj.h" #include "main/texstore.h" #include "main/texformat.h" diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c index ecfbdfedff6..78d29fc485b 100644 --- a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c +++ b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c @@ -277,7 +277,7 @@ nv04_emit_blend(struct gl_context *ctx, int emit) blend |= NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT; /* Secondary color */ - if (NEED_SECONDARY_COLOR(ctx)) + if (_mesa_need_secondary_color(ctx)) blend |= NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE; /* Fog. */ @@ -315,7 +315,7 @@ nv04_emit_blend(struct gl_context *ctx, int emit) blend |= get_texenv_mode(GL_MODULATE); /* Secondary color */ - if (NEED_SECONDARY_COLOR(ctx)) + if (_mesa_need_secondary_color(ctx)) blend |= NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE; /* Fog. */ diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c index e8bd12e6e01..96d1b320d86 100644 --- a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c +++ b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c @@ -199,7 +199,7 @@ nv10_emit_light_model(struct gl_context *ctx, int emit) BEGIN_RING(chan, celsius, NV10_3D_LIGHT_MODEL, 1); OUT_RING(chan, ((m->LocalViewer ? NV10_3D_LIGHT_MODEL_LOCAL_VIEWER : 0) | - (NEED_SECONDARY_COLOR(ctx) ? + (_mesa_need_secondary_color(ctx) ? NV10_3D_LIGHT_MODEL_SEPARATE_SPECULAR : 0) | (!ctx->Light.Enabled && ctx->Fog.ColorSumEnabled ? NV10_3D_LIGHT_MODEL_VERTEX_SPECULAR : 0))); diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c index 4677198dd02..4f7ddd8e49f 100644 --- a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c +++ b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c @@ -178,7 +178,7 @@ nv20_emit_light_model(struct gl_context *ctx, int emit) OUT_RING(chan, ((m->LocalViewer ? NV20_3D_LIGHT_MODEL_VIEWER_LOCAL : NV20_3D_LIGHT_MODEL_VIEWER_NONLOCAL) | - (NEED_SECONDARY_COLOR(ctx) ? + (_mesa_need_secondary_color(ctx) ? NV20_3D_LIGHT_MODEL_SEPARATE_SPECULAR : 0))); diff --git a/src/mesa/drivers/dri/r128/r128_state.c b/src/mesa/drivers/dri/r128/r128_state.c index d6725cdd0ec..7ce082ead22 100644 --- a/src/mesa/drivers/dri/r128/r128_state.c +++ b/src/mesa/drivers/dri/r128/r128_state.c @@ -43,6 +43,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/colormac.h" #include "main/macros.h" +#include "main/state.h" #include "swrast/swrast.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -736,7 +737,7 @@ static void updateSpecularLighting( struct gl_context *ctx ) r128ContextPtr rmesa = R128_CONTEXT(ctx); GLuint t = rmesa->setup.tex_cntl_c; - if ( NEED_SECONDARY_COLOR( ctx ) ) { + if ( _mesa_need_secondary_color( ctx ) ) { if (ctx->Light.ShadeModel == GL_FLAT) { /* R128 can't do flat-shaded separate specular */ t &= ~R128_SPEC_LIGHT_ENABLE; diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c index fa906f2fdde..5223aaa71a4 100644 --- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c +++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c @@ -98,9 +98,6 @@ static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) unsigned int relevant; int j; - if (reg.Abs) - reg.Negate = RC_MASK_NONE; - if (opcode == RC_OPCODE_KIL || opcode == RC_OPCODE_TEX || opcode == RC_OPCODE_TXB || @@ -140,9 +137,6 @@ static void r300_swizzle_split( struct rc_src_register src, unsigned int mask, struct rc_swizzle_split * split) { - if (src.Abs) - src.Negate = RC_MASK_NONE; - split->NumPhases = 0; while(mask) { diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c index 1616306afbd..9286733635f 100644 --- a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c @@ -78,12 +78,32 @@ static void rc_rewrite_depth_out(struct radeon_compiler *cc, void *user) } } +static int radeon_saturate_output( + struct radeon_compiler * c, + struct rc_instruction * inst, + void* data) +{ + const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode); + + if (!info->HasDstReg || inst->U.I.DstReg.File != RC_FILE_OUTPUT) + return 0; + + inst->U.I.SaturateMode = RC_SATURATE_ZERO_ONE; + return 1; +} + void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c) { int is_r500 = c->Base.is_r500; int opt = !c->Base.disable_optimizations; + int sat_out = c->state.frag_clamp; /* Lists of instruction transformations. */ + struct radeon_program_transformation saturate_output[] = { + { &radeon_saturate_output, c }, + { 0, 0 } + }; + struct radeon_program_transformation rewrite_tex[] = { { &radeonTransformTEX, c }, { 0, 0 } @@ -113,6 +133,7 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c) {"unroll loops", 1, is_r500, rc_unroll_loops, NULL}, {"transform loops", 1, !is_r500, rc_transform_loops, NULL}, {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL}, + {"saturate output writes", 1, sat_out, rc_local_transform, saturate_output}, {"transform TEX", 1, 1, rc_local_transform, rewrite_tex}, {"native rewrite", 1, is_r500, rc_local_transform, native_rewrite_r500}, {"native rewrite", 1, !is_r500, rc_local_transform, native_rewrite_r300}, diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c index ef81be48f77..140eeed3de3 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c @@ -77,9 +77,6 @@ static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE)) return 0; - if (reg.Negate) - reg.Negate ^= RC_MASK_XYZW; - for(i = 0; i < 4; ++i) { unsigned int swz = GET_SWZ(reg.Swizzle, i); if (swz == RC_SWIZZLE_UNUSED) { @@ -103,9 +100,6 @@ static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) return 0; } else { /* ALU instructions support almost everything */ - if (reg.Abs) - return 1; - relevant = 0; for(i = 0; i < 3; ++i) { unsigned int swz = GET_SWZ(reg.Swizzle, i); diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c index 1febc19cc2d..301b4446693 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c @@ -372,7 +372,7 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst | (inst->DstReg.WriteMask << 11) | R500_INST_TEX_SEM_WAIT; code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit) - | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED; + | R500_TEX_SEM_ACQUIRE; if (inst->TexSrcTarget == RC_TEXTURE_RECT) code->inst[ip].inst1 |= R500_TEX_UNSCALED; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.h b/src/mesa/drivers/dri/r300/compiler/radeon_code.h index d1451668947..35360aa70f0 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_code.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.h @@ -173,6 +173,8 @@ struct r300_fragment_program_external_state { * RC_STATE_R300_TEXSCALE_FACTOR. */ unsigned clamp_and_scale_before_fetch : 1; } unit[16]; + + unsigned frag_clamp:1; }; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c index 5caff91b00e..c4e6a5e0a1f 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c @@ -311,7 +311,18 @@ static void constant_folding(struct radeon_compiler * c, struct rc_instruction * struct rc_constant * constant; struct rc_src_register newsrc; int have_real_reference; + unsigned int chan; + + /* If there are only 0, 0.5, 1, or _ swizzles, mark the source as a constant. */ + for (chan = 0; chan < 4; ++chan) + if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) <= 3) + break; + if (chan == 4) { + inst->U.I.SrcReg[src].File = RC_FILE_NONE; + continue; + } + /* Convert immediates to swizzles. */ if (inst->U.I.SrcReg[src].File != RC_FILE_CONSTANT || inst->U.I.SrcReg[src].RelAddr || inst->U.I.SrcReg[src].Index >= c->Program.Constants.Count) @@ -325,7 +336,7 @@ static void constant_folding(struct radeon_compiler * c, struct rc_instruction * newsrc = inst->U.I.SrcReg[src]; have_real_reference = 0; - for(unsigned int chan = 0; chan < 4; ++chan) { + for (chan = 0; chan < 4; ++chan) { unsigned int swz = GET_SWZ(newsrc.Swizzle, chan); unsigned int newswz; float imm; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c index 6d7263b4ab6..9e03eb1aca8 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c @@ -214,16 +214,21 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c, if (needrgb && !istranscendent) { unsigned int srcrgb = 0; unsigned int srcalpha = 0; + unsigned int srcmask = 0; int j; /* We don't care about the alpha channel here. We only * want the part of the swizzle that writes to rgb, * since we are creating an rgb instruction. */ for(j = 0; j < 3; ++j) { unsigned int swz = GET_SWZ(inst->SrcReg[i].Swizzle, j); - if (swz < 3) + + if (swz < RC_SWIZZLE_W) srcrgb = 1; - else if (swz < 4) + else if (swz == RC_SWIZZLE_W) srcalpha = 1; + + if (swz < RC_SWIZZLE_UNUSED) + srcmask |= 1 << j; } source = rc_pair_alloc_source(pair, srcrgb, srcalpha, inst->SrcReg[i].File, inst->SrcReg[i].Index); @@ -236,7 +241,7 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c, pair->RGB.Arg[i].Swizzle = rc_init_swizzle(inst->SrcReg[i].Swizzle, 3); pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs; - pair->RGB.Arg[i].Negate = !!(inst->SrcReg[i].Negate & (RC_MASK_X | RC_MASK_Y | RC_MASK_Z)); + pair->RGB.Arg[i].Negate = !!(srcmask & inst->SrcReg[i].Negate & (RC_MASK_X | RC_MASK_Y | RC_MASK_Z)); } if (needalpha) { unsigned int srcrgb = 0; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c index f9d9f34b6ad..1cf77d9cf73 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c @@ -33,14 +33,14 @@ /* Series of transformations to be done on textures. */ static struct rc_src_register shadow_ambient(struct r300_fragment_program_compiler *compiler, - int tmu) + int tmu) { struct rc_src_register reg = { 0, }; if (compiler->enable_shadow_ambient) { reg.File = RC_FILE_CONSTANT; reg.Index = rc_constants_add_state(&compiler->Base.Program.Constants, - RC_STATE_SHADOW_AMBIENT, tmu); + RC_STATE_SHADOW_AMBIENT, tmu); reg.Swizzle = RC_SWIZZLE_WWWW; } else { reg.File = RC_FILE_NONE; @@ -149,14 +149,11 @@ int radeonTransformTEX( return 1; } else { - rc_compare_func comparefunc = compiler->state.unit[inst->U.I.TexSrcUnit].texture_compare_func; struct rc_instruction * inst_rcp = NULL; - struct rc_instruction * inst_mad; - struct rc_instruction * inst_cmp; + struct rc_instruction *inst_mul, *inst_add, *inst_cmp; unsigned tmp_texsample; unsigned tmp_sum; - unsigned tmp_recip_w = 0; - int pass, fail, tex; + int pass, fail; /* Save the output register. */ struct rc_dst_register output_reg = inst->U.I.DstReg; @@ -167,63 +164,68 @@ int radeonTransformTEX( inst->U.I.DstReg.Index = tmp_texsample; inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; - if (inst->U.I.Opcode == RC_OPCODE_TXP) { - tmp_recip_w = rc_find_free_temporary(c); + tmp_sum = rc_find_free_temporary(c); + if (inst->U.I.Opcode == RC_OPCODE_TXP) { /* Compute 1/W. */ inst_rcp = rc_insert_new_instruction(c, inst); inst_rcp->U.I.Opcode = RC_OPCODE_RCP; inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; - inst_rcp->U.I.DstReg.Index = tmp_recip_w; + inst_rcp->U.I.DstReg.Index = tmp_sum; inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; inst_rcp->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 3)); } - /* Perspective-divide Z by W (if it's TXP) and add the texture sample (see below). */ - tmp_sum = rc_find_free_temporary(c); - inst_mad = rc_insert_new_instruction(c, inst_rcp ? inst_rcp : inst); - inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY; - inst_mad->U.I.DstReg.Index = tmp_sum; - inst_mad->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; - inst_mad->U.I.SrcReg[0].Swizzle = + /* Divide Z by W (if it's TXP) and saturate. */ + inst_mul = rc_insert_new_instruction(c, inst_rcp ? inst_rcp : inst); + inst_mul->U.I.Opcode = inst->U.I.Opcode == RC_OPCODE_TXP ? RC_OPCODE_MUL : RC_OPCODE_MOV; + inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; + inst_mul->U.I.DstReg.Index = tmp_sum; + inst_mul->U.I.DstReg.WriteMask = RC_MASK_W; + inst_mul->U.I.SaturateMode = RC_SATURATE_ZERO_ONE; + inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; + inst_mul->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 2)); if (inst->U.I.Opcode == RC_OPCODE_TXP) { - inst_mad->U.I.Opcode = RC_OPCODE_MAD; - inst_mad->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; - inst_mad->U.I.SrcReg[1].Index = tmp_recip_w; - inst_mad->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW; - tex = 2; - } else { - inst_mad->U.I.Opcode = RC_OPCODE_ADD; - tex = 1; - } - inst_mad->U.I.SrcReg[tex].File = RC_FILE_TEMPORARY; - inst_mad->U.I.SrcReg[tex].Index = tmp_texsample; - inst_mad->U.I.SrcReg[tex].Swizzle = compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_swizzle; - - /* Fake EQUAL/NOTEQUAL, it seems to pass some tests suprisingly. */ - if (comparefunc == RC_COMPARE_FUNC_EQUAL) { - comparefunc = RC_COMPARE_FUNC_GEQUAL; - } else if (comparefunc == RC_COMPARE_FUNC_NOTEQUAL) { - comparefunc = RC_COMPARE_FUNC_LESS; + inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; + inst_mul->U.I.SrcReg[1].Index = tmp_sum; + inst_mul->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW; } - /* Recall that SrcReg[0] is r, SrcReg[tex] is tex and: + /* Add the depth texture value. */ + inst_add = rc_insert_new_instruction(c, inst_mul); + inst_add->U.I.Opcode = RC_OPCODE_ADD; + inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; + inst_add->U.I.DstReg.Index = tmp_sum; + inst_add->U.I.DstReg.WriteMask = RC_MASK_W; + inst_add->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; + inst_add->U.I.SrcReg[0].Index = tmp_sum; + inst_add->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW; + inst_add->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; + inst_add->U.I.SrcReg[1].Index = tmp_texsample; + inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XXXX; + + /* Note that SrcReg[0] is r, SrcReg[1] is tex and: * LESS: r < tex <=> -tex+r < 0 * GEQUAL: r >= tex <=> not (-tex+r < 0) * GREATER: r > tex <=> tex-r < 0 * LEQUAL: r <= tex <=> not ( tex-r < 0) - * - * This negates either r or tex: */ - if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GEQUAL) - inst_mad->U.I.SrcReg[tex].Negate = inst_mad->U.I.SrcReg[tex].Negate ^ RC_MASK_XYZW; + * EQUAL: GEQUAL + * NOTEQUAL:LESS + */ + + /* This negates either r or tex: */ + if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GEQUAL || + comparefunc == RC_COMPARE_FUNC_EQUAL || comparefunc == RC_COMPARE_FUNC_NOTEQUAL) + inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; else - inst_mad->U.I.SrcReg[0].Negate = inst_mad->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; + inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; /* This negates the whole expresion: */ - if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GREATER) { + if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GREATER || + comparefunc == RC_COMPARE_FUNC_NOTEQUAL) { pass = 1; fail = 2; } else { @@ -231,16 +233,19 @@ int radeonTransformTEX( fail = 1; } - inst_cmp = rc_insert_new_instruction(c, inst_mad); + inst_cmp = rc_insert_new_instruction(c, inst_add); inst_cmp->U.I.Opcode = RC_OPCODE_CMP; inst_cmp->U.I.DstReg = output_reg; inst_cmp->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; inst_cmp->U.I.SrcReg[0].Index = tmp_sum; + inst_cmp->U.I.SrcReg[0].Swizzle = + combine_swizzles(RC_SWIZZLE_WWWW, + compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_swizzle); inst_cmp->U.I.SrcReg[pass].File = RC_FILE_NONE; inst_cmp->U.I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111; inst_cmp->U.I.SrcReg[fail] = shadow_ambient(compiler, inst->U.I.TexSrcUnit); - assert(tmp_texsample != tmp_sum && tmp_sum != tmp_recip_w); + assert(tmp_texsample != tmp_sum); } } @@ -420,17 +425,21 @@ int radeonTransformTEX( scale_texcoords(compiler, inst, RC_STATE_R300_TEXSCALE_FACTOR); } - /* Cannot write texture to output registers (all chips) or with masks (non-r500) */ + /* Cannot write texture to output registers or with saturate (all chips), + * or with masks (non-r500). */ if (inst->U.I.Opcode != RC_OPCODE_KIL && (inst->U.I.DstReg.File != RC_FILE_TEMPORARY || + inst->U.I.SaturateMode || (!c->is_r500 && inst->U.I.DstReg.WriteMask != RC_MASK_XYZW))) { struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst); inst_mov->U.I.Opcode = RC_OPCODE_MOV; + inst_mov->U.I.SaturateMode = inst->U.I.SaturateMode; inst_mov->U.I.DstReg = inst->U.I.DstReg; inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; inst_mov->U.I.SrcReg[0].Index = rc_find_free_temporary(c); + inst->U.I.SaturateMode = 0; inst->U.I.DstReg.File = RC_FILE_TEMPORARY; inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index; inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 9df9101bcd3..51989c6b224 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -214,7 +214,7 @@ static void r300SetBlendState(struct gl_context * ctx) (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT); int eqnA = R300_COMB_FCN_ADD_CLAMP; - if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { + if (_mesa_rgba_logicop_enabled(ctx) || !ctx->Color.BlendEnabled) { r300SetBlendCntl(r300, func, eqn, 0, func, eqn); return; } @@ -335,7 +335,7 @@ static void r300SetLogicOpState(struct gl_context *ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); R300_STATECHANGE(r300, rop); - if (RGBA_LOGICOP_ENABLED(ctx)) { + if (_mesa_rgba_logicop_enabled(ctx)) { r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE | translate_logicop(ctx->Color.LogicOp); } else { @@ -349,7 +349,7 @@ static void r300SetLogicOpState(struct gl_context *ctx) */ static void r300LogicOpcode(struct gl_context *ctx, GLenum logicop) { - if (RGBA_LOGICOP_ENABLED(ctx)) + if (_mesa_rgba_logicop_enabled(ctx)) r300SetLogicOpState(ctx); } diff --git a/src/mesa/drivers/dri/r600/evergreen_state.c b/src/mesa/drivers/dri/r600/evergreen_state.c index 006e50007b6..309c93fe088 100644 --- a/src/mesa/drivers/dri/r600/evergreen_state.c +++ b/src/mesa/drivers/dri/r600/evergreen_state.c @@ -32,6 +32,7 @@ #include "main/context.h" #include "main/dd.h" #include "main/simple_list.h" +#include "main/state.h" #include "tnl/tnl.h" #include "tnl/t_pipeline.h" @@ -342,7 +343,7 @@ static void evergreenSetBlendState(struct gl_context * ctx) //diff : CB_COLOR_CO EVERGREEN_STATECHANGE(context, cb); - if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { + if (_mesa_rgba_logicop_enabled(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask); SETfield(blend_reg, @@ -520,7 +521,7 @@ static void evergreenSetLogicOpState(struct gl_context *ctx) //diff : CB_COLOR_C EVERGREEN_STATECHANGE(context, cb); - if (RGBA_LOGICOP_ENABLED(ctx)) + if (_mesa_rgba_logicop_enabled(ctx)) SETfield(evergreen->CB_COLOR_CONTROL.u32All, evergreen_translate_logicop(ctx->Color.LogicOp), EG_CB_COLOR_CONTROL__ROP3_shift, @@ -1148,7 +1149,7 @@ static void evergreenShadeModel(struct gl_context * ctx, GLenum mode) //same static void evergreenLogicOpcode(struct gl_context *ctx, GLenum logicop) //diff { - if (RGBA_LOGICOP_ENABLED(ctx)) + if (_mesa_rgba_logicop_enabled(ctx)) evergreenSetLogicOpState(ctx); } diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index f8770690ff6..4d285b36489 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -32,6 +32,7 @@ #include "main/context.h" #include "main/dd.h" #include "main/simple_list.h" +#include "main/state.h" #include "tnl/tnl.h" #include "tnl/t_pipeline.h" @@ -453,7 +454,7 @@ static void r700SetBlendState(struct gl_context * ctx) R600_STATECHANGE(context, blnd); - if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { + if (_mesa_rgba_logicop_enabled(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask); SETfield(blend_reg, @@ -644,7 +645,7 @@ static void r700SetLogicOpState(struct gl_context *ctx) R600_STATECHANGE(context, blnd); - if (RGBA_LOGICOP_ENABLED(ctx)) + if (_mesa_rgba_logicop_enabled(ctx)) SETfield(r700->CB_COLOR_CONTROL.u32All, translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask); else @@ -657,7 +658,7 @@ static void r700SetLogicOpState(struct gl_context *ctx) */ static void r700LogicOpcode(struct gl_context *ctx, GLenum logicop) { - if (RGBA_LOGICOP_ENABLED(ctx)) + if (_mesa_rgba_logicop_enabled(ctx)) r700SetLogicOpState(ctx); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index e88e984354f..a93e61870a5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -40,6 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/framebuffer.h" #include "main/simple_list.h" +#include "main/state.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -661,7 +662,7 @@ static void radeonUpdateSpecular( struct gl_context *ctx ) TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_FOGCOORDSPEC, flag); - if (NEED_SECONDARY_COLOR(ctx)) { + if (_mesa_need_secondary_color(ctx)) { assert( (p & RADEON_SPECULAR_ENABLE) != 0 ); } else { assert( (p & RADEON_SPECULAR_ENABLE) == 0 ); diff --git a/src/mesa/drivers/dri/savage/savagestate.c b/src/mesa/drivers/dri/savage/savagestate.c index 1feffa0b0a2..21ebf5dc2b2 100644 --- a/src/mesa/drivers/dri/savage/savagestate.c +++ b/src/mesa/drivers/dri/savage/savagestate.c @@ -29,8 +29,9 @@ #include "main/enums.h" #include "main/macros.h" #include "main/dd.h" - #include "main/mm.h" +#include "main/state.h" + #include "savagedd.h" #include "savagecontext.h" @@ -869,7 +870,7 @@ static void savageUpdateSpecular_s4(struct gl_context *ctx) { savageContextPtr imesa = SAVAGE_CONTEXT( ctx ); uint32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui; - if (NEED_SECONDARY_COLOR(ctx)) { + if (_mesa_need_secondary_color(ctx)) { imesa->regs.s4.drawLocalCtrl.ni.specShadeEn = GL_TRUE; } else { imesa->regs.s4.drawLocalCtrl.ni.specShadeEn = GL_FALSE; @@ -883,7 +884,7 @@ static void savageUpdateSpecular_s3d(struct gl_context *ctx) { savageContextPtr imesa = SAVAGE_CONTEXT( ctx ); uint32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui; - if (NEED_SECONDARY_COLOR(ctx)) { + if (_mesa_need_secondary_color(ctx)) { imesa->regs.s3d.drawCtrl.ni.specShadeEn = GL_TRUE; } else { imesa->regs.s3d.drawCtrl.ni.specShadeEn = GL_FALSE; diff --git a/src/mesa/drivers/dri/sis/sis6326_state.c b/src/mesa/drivers/dri/sis/sis6326_state.c index 9708f639124..9ca58293b43 100644 --- a/src/mesa/drivers/dri/sis/sis6326_state.c +++ b/src/mesa/drivers/dri/sis/sis6326_state.c @@ -35,6 +35,7 @@ #include "main/context.h" #include "main/colormac.h" +#include "main/state.h" #include "swrast/swrast.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -355,7 +356,7 @@ static void sis6326UpdateSpecular(struct gl_context *ctx) sisContextPtr smesa = SIS_CONTEXT(ctx); __GLSiSHardware *current = &smesa->current; - if (NEED_SECONDARY_COLOR(ctx)) + if (_mesa_need_secondary_color(ctx)) current->hwCapEnable |= S_ENABLE_Specular; else current->hwCapEnable &= ~S_ENABLE_Specular; diff --git a/src/mesa/drivers/dri/sis/sis_state.c b/src/mesa/drivers/dri/sis/sis_state.c index e53c326441b..828772ed6ef 100644 --- a/src/mesa/drivers/dri/sis/sis_state.c +++ b/src/mesa/drivers/dri/sis/sis_state.c @@ -38,6 +38,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/macros.h" +#include "main/state.h" #include "swrast/swrast.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -407,7 +408,7 @@ static void sisUpdateSpecular(struct gl_context *ctx) sisContextPtr smesa = SIS_CONTEXT(ctx); __GLSiSHardware *current = &smesa->current; - if (NEED_SECONDARY_COLOR(ctx)) + if (_mesa_need_secondary_color(ctx)) current->hwCapEnable |= MASK_SpecularEnable; else current->hwCapEnable &= ~MASK_SpecularEnable; |