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-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_fast_clear.c6
2 files changed, 7 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 12314204803..1d4ba3cac7e 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -121,8 +121,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
* first.
*/
if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(ctx, fb)) {
- perf_debug("Failed to fast clear depth due to scissor being enabled. "
- "Possible 5%% performance win if avoided.\n");
+ perf_debug("Failed to fast clear %dx%d depth because of scissors. "
+ "Possible 5%% performance win if avoided.\n",
+ mt->logical_width0, mt->logical_height0);
return false;
}
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 06916e28cbd..a864143e6dc 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -466,7 +466,8 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* linear (untiled) memory is UNDEFINED."
*/
if (irb->mt->tiling == I915_TILING_NONE) {
- perf_debug("falling back to plain clear because buffers are untiled\n");
+ perf_debug("Falling back to plain clear because %dx%d buffer is untiled\n",
+ irb->mt->logical_width0, irb->mt->logical_height0);
clear_type = PLAIN_CLEAR;
}
@@ -477,7 +478,8 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
for (int i = 0; i < 4; i++) {
if (_mesa_format_has_color_component(irb->mt->format, i) &&
!color_mask[i]) {
- perf_debug("falling back to plain clear because of color mask\n");
+ perf_debug("Falling back to plain clear on %dx%d buffer because of color mask\n",
+ irb->mt->logical_width0, irb->mt->logical_height0);
clear_type = PLAIN_CLEAR;
}
}