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-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h24
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c36
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c6
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c28
-rw-r--r--src/mesa/drivers/dri/i965/gen7_sf_state.c4
7 files changed, 53 insertions, 55 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 22a6826420f..1d2ef066db2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -138,7 +138,6 @@ enum brw_state_id {
BRW_STATE_INDICES,
BRW_STATE_VERTICES,
BRW_STATE_BATCH,
- BRW_STATE_DEPTH_BUFFER,
BRW_STATE_NR_WM_SURFACES,
BRW_STATE_NR_VS_SURFACES,
BRW_STATE_INDEX_BUFFER,
@@ -168,7 +167,6 @@ enum brw_state_id {
*/
#define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
/** \see brw.state.depth_region */
-#define BRW_NEW_DEPTH_BUFFER (1 << BRW_STATE_DEPTH_BUFFER)
#define BRW_NEW_NR_WM_SURFACES (1 << BRW_STATE_NR_WM_SURFACES)
#define BRW_NEW_NR_VS_SURFACES (1 << BRW_STATE_NR_VS_SURFACES)
#define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
@@ -490,28 +488,6 @@ struct brw_context
struct {
struct brw_state_flags dirty;
-
- /**
- * \name Cached region pointers
- *
- * When the draw buffer is updated, often the depth buffer is not
- * changed. Caching the pointer to the buffer's region allows us to
- * detect when the buffer has in fact changed, and allows us to avoid
- * updating the buffer's GPU state when it has not.
- *
- * The original of each cached pointer is an instance of
- * \c intel_renderbuffer.region.
- *
- * \see brw_set_draw_region()
- *
- * \{
- */
-
- /** \see struct brw_tracked_state brw_depthbuffer */
- struct intel_region *depth_region;
-
- /** \} */
-
/**
* List of buffers accumulated in brw_validate_state to receive
* drm_intel_bo_check_aperture treatment before exec, so we can
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index cb2814b6eff..938f6cf070d 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -32,6 +32,7 @@
#include "intel_batchbuffer.h"
+#include "intel_fbo.h"
#include "intel_regions.h"
#include "brw_context.h"
@@ -193,18 +194,33 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
static void prepare_depthbuffer(struct brw_context *brw)
{
- struct intel_region *region = brw->state.depth_region;
-
- if (region != NULL)
- brw_add_validated_bo(brw, region->buffer);
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
+ if (drb)
+ brw_add_validated_bo(brw, drb->region->buffer);
+ if (srb)
+ brw_add_validated_bo(brw, srb->region->buffer);
}
static void emit_depthbuffer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- struct intel_region *region = brw->state.depth_region;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ /* _NEW_BUFFERS */
+ struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
unsigned int len;
+ /* If we're combined depth stencil but no depth is attached, look
+ * up stencil.
+ */
+ if (!irb)
+ irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
if (intel->gen >= 6)
len = 7;
else if (intel->is_g4x || intel->gen == 5)
@@ -212,7 +228,7 @@ static void emit_depthbuffer(struct brw_context *brw)
else
len = 5;
- if (region == NULL) {
+ if (!irb) {
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -229,6 +245,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
+ struct intel_region *region = irb->region;
unsigned int format;
switch (region->cpp) {
@@ -282,13 +299,10 @@ static void emit_depthbuffer(struct brw_context *brw)
}
}
-/**
- * \see brw_context.state.depth_region
- */
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
- .mesa = 0,
- .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
+ .mesa = _NEW_BUFFERS,
+ .brw = BRW_NEW_BATCH,
.cache = 0,
},
.prepare = prepare_depthbuffer,
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f4a7048f525..6a4c112dcf5 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -371,7 +371,6 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
DEFINE_BIT(BRW_NEW_VERTICES),
DEFINE_BIT(BRW_NEW_BATCH),
- DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 28d5f62f34b..9f99ef57214 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -68,8 +68,6 @@ static void brw_destroy_context( struct intel_context *intel )
brw_clear_validated_bos(brw);
ralloc_free(brw->wm.compile_data);
- intel_region_release(&brw->state.depth_region);
-
dri_bo_release(&brw->curbe.curbe_bo);
dri_bo_release(&brw->vs.prog_bo);
dri_bo_release(&brw->vs.const_bo);
@@ -93,13 +91,6 @@ static void brw_set_draw_region( struct intel_context *intel,
struct intel_region *depth_region,
GLuint num_color_regions)
{
- struct brw_context *brw = brw_context(&intel->ctx);
-
- if (brw->state.depth_region != depth_region) {
- brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
- intel_region_release(&brw->state.depth_region);
- intel_region_reference(&brw->state.depth_region, depth_region);
- }
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index a91ae511b7f..a356711470a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
+#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@@ -144,11 +145,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
(1 << FRAG_ATTRIB_WPOS)) != 0;
wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
- /* BRW_NEW_DEPTH_BUFFER
+ /* _NEW_BUFFERS
* Override for NULL depthbuffer case, required by the Pixel Shader Computed
* Depth field.
*/
- if (brw->state.depth_region == NULL)
+ if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
wm->wm5.program_computes_depth = 0;
/* _NEW_COLOR */
@@ -266,7 +267,6 @@ const struct brw_tracked_state brw_wm_unit = {
.brw = (BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_CURBE_OFFSETS |
- BRW_NEW_DEPTH_BUFFER |
BRW_NEW_NR_WM_SURFACES),
.cache = (CACHE_NEW_WM_PROG |
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index adcb31f7a95..68a222eb3fb 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -23,6 +23,7 @@
#include "intel_batchbuffer.h"
#include "intel_regions.h"
+#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@@ -30,10 +31,18 @@
unsigned int
gen7_depth_format(struct brw_context *brw)
{
- struct intel_region *region = brw->state.depth_region;
struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ struct intel_region *region = NULL;
- if (region == NULL)
+ if (drb)
+ region = drb->region;
+ else if (srb)
+ region = srb->region;
+ else
return BRW_DEPTHFORMAT_D32_FLOAT;
switch (region->cpp) {
@@ -52,9 +61,18 @@ gen7_depth_format(struct brw_context *brw)
static void emit_depthbuffer(struct brw_context *brw)
{
- struct intel_region *region = brw->state.depth_region;
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ struct intel_region *region = NULL;
+
+ /* _NEW_BUFFERS */
+ if (drb)
+ region = drb->region;
+ else if (srb)
+ region = srb->region;
if (region == NULL) {
BEGIN_BATCH(7);
@@ -114,8 +132,8 @@ static void emit_depthbuffer(struct brw_context *brw)
*/
const struct brw_tracked_state gen7_depthbuffer = {
.dirty = {
- .mesa = 0,
- .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
+ .mesa = _NEW_BUFFERS,
+ .brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = emit_depthbuffer,
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index d1bf8a81874..99efe96a1fa 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -128,6 +128,7 @@ upload_sf_state(struct brw_context *brw)
dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
+ /* _NEW_BUFFERS */
dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
/* _NEW_POLYGON */
@@ -258,8 +259,7 @@ const struct brw_tracked_state gen7_sf_state = {
_NEW_SCISSOR |
_NEW_BUFFERS |
_NEW_POINT),
- .brw = (BRW_NEW_CONTEXT |
- BRW_NEW_DEPTH_BUFFER),
+ .brw = (BRW_NEW_CONTEXT),
.cache = CACHE_NEW_VS_PROG
},
.emit = upload_sf_state,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 06:06:25 +0000