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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c5
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 76ec9a26a27..5a9e77576ec 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1660,6 +1660,10 @@ enum brw_pixel_shader_coverage_mask_mode {
# define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7)
# define GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE (1 << 11)
+
+#define COMMON_SLICE_CHICKEN4 0x7300
+# define GEN11_ENABLE_HARDWARE_FILTERING_IN_WM (1 << 5)
+
#define HALF_SLICE_CHICKEN7 0xE194
# define TEXEL_OFFSET_FIX_ENABLE (1 << 1)
# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 1)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 87e459376a8..dfbcea586cc 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -189,6 +189,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
*/
brw_load_register_imm32(brw, GEN8_L3CNTLREG,
GEN8_L3CNTLREG_EDBC_NO_HANG);
+
+ /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */
+ brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN4,
+ GEN11_ENABLE_HARDWARE_FILTERING_IN_WM |
+ REG_MASK(GEN11_ENABLE_HARDWARE_FILTERING_IN_WM));
}
/* hardware specification recommends disabling repacking for