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-rw-r--r--src/mesa/drivers/dri/r600/r600_reg_r7xx.h2
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c4
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_reg_r7xx.h b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h
index e5c01c861aa..eb169bd885d 100644
--- a/src/mesa/drivers/dri/r600/r600_reg_r7xx.h
+++ b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h
@@ -143,6 +143,8 @@ enum {
// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
R7xx_TRUNCATE_COORD_bit = 1 << 9,
R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
+// DB_RENDER_CONTROL = 0x00028d0c,
+ PERFECT_ZPASS_COUNTS_bit = 1 << 15,
} ;
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index b2788872666..b95fc87d309 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1686,6 +1686,10 @@ void r700InitState(GLcontext * ctx) //-------------------
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ {
+ CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
+ }
r700->DB_ALPHA_TO_MASK.u32All = 0;
SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);