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-rw-r--r--src/mesa/drivers/dri/r300/r300_texstate.c20
-rw-r--r--src/mesa/drivers/dri/r300/r300_vertprog.c12
-rw-r--r--src/mesa/drivers/dri/r600/r600_cmdbuf.c18
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c12
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c13
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_bo_legacy.c4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_fbo.c5
7 files changed, 51 insertions, 33 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index f030451b282..65cabccdc1e 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -225,10 +225,10 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
if (t->image_override && t->bo)
return;
- t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)
- | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)
- | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)
- | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT));
+ t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
+ | ((R300_TX_HEIGHTMASK_MASK & ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)))
+ | ((R300_TX_DEPTHMASK_MASK & ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)))
+ | ((R300_TX_MAX_MIP_LEVEL_MASK & ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT))));
t->tile_bits = 0;
@@ -248,8 +248,12 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (firstImage->Width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
+ else
+ t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
if (firstImage->Height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
+ else
+ t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
}
}
@@ -479,16 +483,20 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
break;
}
pitch_val--;
- t->pp_txsize = ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT) |
- ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT);
+ t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
+ | ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT))));
t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
t->pp_txpitch |= pitch_val;
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (rb->base.Width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
+ else
+ t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
if (rb->base.Height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
+ else
+ t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
}
t->validated = GL_TRUE;
_mesa_unlock_texture(radeon->glCtx, texObj);
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c
index 43629d643bc..c2f96af2c12 100644
--- a/src/mesa/drivers/dri/r300/r300_vertprog.c
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.c
@@ -62,12 +62,6 @@ static int r300VertexProgUpdateParams(GLcontext * ctx, struct r300_vertex_progra
}
}
- if (vp->code.constants.Count * 4 > VSF_MAX_FRAGMENT_LENGTH) {
- /* Should have checked this earlier... */
- fprintf(stderr, "%s:Params exhausted\n", __FUNCTION__);
- _mesa_exit(-1);
- }
-
for(i = 0; i < vp->code.constants.Count; ++i) {
const float * src = 0;
const struct rc_constant * constant = &vp->code.constants.Constants[i];
@@ -281,6 +275,11 @@ static struct r300_vertex_program *build_program(GLcontext *ctx,
}
r3xx_compile_vertex_program(&compiler);
+
+ if (vp->code.constants.Count > ctx->Const.VertexProgram.MaxParameters) {
+ rc_error(&compiler.Base, "Program exceeds constant buffer size limit\n");
+ }
+
vp->error = compiler.Base.Error;
vp->Base->Base.InputsRead = vp->code.InputsRead;
@@ -334,7 +333,6 @@ struct r300_vertex_program * r300SelectAndTranslateVertexShader(GLcontext *ctx)
#define bump_vpu_count(ptr, new_count) do { \
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \
int _nc=(new_count)/4; \
- assert(_nc < 256); \
if(_nc>_p->vpu.count)_p->vpu.count=_nc; \
} while(0)
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 3cfe03a45f7..d27a3245a39 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -254,7 +254,7 @@ static int r600_cs_process_relocs(struct radeon_cs *cs,
relocs = (struct r600_cs_reloc_legacy *)cs->relocs;
restart:
for (i = 0; i < cs->crelocs; i++) {
- uint32_t soffset, eoffset, asicoffset;
+ uint32_t soffset, eoffset;
r = radeon_bo_legacy_validate(relocs[i].base.bo,
&soffset, &eoffset);
@@ -262,24 +262,12 @@ restart:
goto restart;
}
if (r) {
- fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
+ fprintf(stderr, "invalid bo(%p) [0x%08X, 0x%08X]\n",
relocs[i].base.bo, soffset, eoffset);
return r;
}
- asicoffset = soffset;
for (j = 0; j < relocs[i].cindices; j++) {
- if (asicoffset >= eoffset) {
- /* radeon_bo_debug(relocs[i].base.bo, 12); */
- fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
- relocs[i].base.bo, soffset, eoffset);
- fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
- relocs[i].base.bo,
- cs->packets[relocs[i].indices[j]],
- eoffset);
- exit(0);
- return -EINVAL;
- }
/* pkt3 nop header in ib chunk */
cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000;
/* reloc index in ib chunk */
@@ -287,7 +275,7 @@ restart:
}
/* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
- reloc_chunk[offset_dw] = asicoffset;
+ reloc_chunk[offset_dw] = soffset;
reloc_chunk[offset_dw + 3] = 0;
offset_dw += 4;
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 7d7e77d355b..ba1371bf95a 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -764,7 +764,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
radeonTexObjPtr t = radeon_tex_obj(tObj);
- uint32_t pitch_val, size;
+ int firstlevel = t->mt ? t->mt->firstLevel : 0;
+ const struct gl_texture_image *firstImage;
+ uint32_t pitch_val, size, row_align, bpp;
if (!tObj)
return;
@@ -774,7 +776,13 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
if (!offset)
return;
- size = pitch;//h * w * (depth / 8);
+ bpp = depth / 8;
+ if (bpp == 3)
+ bpp = 4;
+
+ firstImage = t->base.Image[0][firstlevel];
+ row_align = rmesa->radeon.texture_row_align - 1;
+ size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height;
if (t->bo) {
radeon_bo_unref(t->bo);
t->bo = NULL;
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index ed597c027b5..e07f9baa05b 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1307,8 +1307,10 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
case PROGRAM_INPUT:
switch (pILInst->SrcReg[0].Index)
{
+ case FRAG_ATTRIB_WPOS:
case FRAG_ATTRIB_COL0:
case FRAG_ATTRIB_COL1:
+ case FRAG_ATTRIB_FOGC:
case FRAG_ATTRIB_TEX0:
case FRAG_ATTRIB_TEX1:
case FRAG_ATTRIB_TEX2:
@@ -1321,7 +1323,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
pAsm->S[0].src.reg =
pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
pAsm->S[0].src.rtype = SRC_REG_INPUT;
- break;
+ break;
+ case FRAG_ATTRIB_FACE:
+ fprintf(stderr, "FRAG_ATTRIB_FACE unsupported\n");
+ break;
+ case FRAG_ATTRIB_PNTC:
+ fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n");
+ break;
+ case FRAG_ATTRIB_VAR0:
+ fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n");
+ break;
}
break;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index 3e7547d2f9d..ce60a2f7eae 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -710,6 +710,10 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo,
bo, bo->size, bo_legacy->map_count);
return -EINVAL;
}
+ if(bo->size == 0) {
+ fprintf(stderr, "bo(%p) has size 0.\n", bo);
+ return -EINVAL;
+ }
if (bo_legacy->static_bo || bo_legacy->validated) {
*soffset = bo_legacy->offset;
*eoffset = bo_legacy->offset + bo->size;
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 7ac53ec0ca3..0ae906a6cea 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -445,7 +445,6 @@ restart:
goto restart;
}
- rrb->pitch = texImage->Width * rrb->cpp;
rrb->base.InternalFormat = rrb->base._ActualFormat;
rrb->base.Width = texImage->Width;
rrb->base.Height = texImage->Height;
@@ -555,8 +554,10 @@ radeon_render_texture(GLcontext * ctx,
imageOffset += offsets[att->Zoffset];
}
- /* store that offset in the region */
+ /* store that offset in the region, along with the correct pitch for
+ * the image we are rendering to */
rrb->draw_offset = imageOffset;
+ rrb->pitch = radeon_image->mt->levels[att->TextureLevel].rowstride;
/* update drawing region, etc */
radeon_draw_buffer(ctx, fb);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 11:43:12 +0000