diff options
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 11 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 855f1c7d744..433314115b1 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode { # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7) # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7) +#define GEN11_SAMPLER_MODE 0xE18C +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS (1 << 5) +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK REG_MASK(1 << 5) + #endif diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 757426407c3..2af4c45bc44 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); + if (devinfo->gen == 11) { + /* The default behavior of bit 5 "Headerless Message for Pre-emptable + * Contexts" in SAMPLER MODE register is set to 0, which means + * headerless sampler messages are not allowed for pre-emptable + * contexts. Set the bit 5 to 1 to allow them. + */ + brw_load_register_imm32(brw, GEN11_SAMPLER_MODE, + HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK | + HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS); + } + if (devinfo->gen == 10 || devinfo->gen == 11) { /* From gen10 workaround table in h/w specs: * |