diff options
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.h | 14 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 111 |
3 files changed, 39 insertions, 104 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index d38be8aa79b..96201e46aea 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -70,7 +70,6 @@ brw_blorp_surface_info_init(struct brw_context *brw, &info->x_offset, &info->y_offset); info->array_layout = mt->array_layout; - info->msaa_layout = mt->msaa_layout; info->swizzle = SWIZZLE_XYZW; if (format == MESA_FORMAT_NONE) @@ -210,22 +209,6 @@ brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir, return program; } -static enum isl_msaa_layout -get_isl_msaa_layout(enum intel_msaa_layout layout) -{ - switch (layout) { - case INTEL_MSAA_LAYOUT_NONE: - return ISL_MSAA_LAYOUT_NONE; - case INTEL_MSAA_LAYOUT_IMS: - return ISL_MSAA_LAYOUT_INTERLEAVED; - case INTEL_MSAA_LAYOUT_UMS: - case INTEL_MSAA_LAYOUT_CMS: - return ISL_MSAA_LAYOUT_ARRAY; - default: - unreachable("Invalid MSAA layout"); - } -} - struct surface_state_info { unsigned num_dwords; unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */ @@ -255,7 +238,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw, /* Stomp surface dimensions and tiling (if needed) with info from blorp */ surf.dim = ISL_SURF_DIM_2D; surf.dim_layout = ISL_DIM_LAYOUT_GEN4_2D; - surf.msaa_layout = get_isl_msaa_layout(surface->msaa_layout); surf.logical_level0_px.width = surface->width; surf.logical_level0_px.height = surface->height; surf.logical_level0_px.depth = 1; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 0f142b41264..d60b9887368 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -134,12 +134,6 @@ struct brw_blorp_surface_info uint32_t brw_surfaceformat; /** - * For MSAA surfaces, MSAA layout that should be used when setting up the - * surface state for this surface. - */ - enum intel_msaa_layout msaa_layout; - - /** * In order to support cases where RGBA format is backing client requested * RGB, one needs to have means to force alpha channel to one when user * requested RGB surface is used as blit source. This is possible by @@ -298,7 +292,7 @@ struct brw_blorp_blit_prog_key /* MSAA layout that has been configured in the surface state for texturing * from. */ - enum intel_msaa_layout tex_layout; + enum isl_msaa_layout tex_layout; enum isl_aux_usage tex_aux_usage; @@ -306,7 +300,7 @@ struct brw_blorp_blit_prog_key unsigned src_samples; /* Actual MSAA layout used by the source image. */ - enum intel_msaa_layout src_layout; + enum isl_msaa_layout src_layout; /* Number of samples per pixel that have been configured in the render * target. @@ -314,13 +308,13 @@ struct brw_blorp_blit_prog_key unsigned rt_samples; /* MSAA layout that has been configured in the render target. */ - enum intel_msaa_layout rt_layout; + enum isl_msaa_layout rt_layout; /* Actual number of samples per pixel in the destination image. */ unsigned dst_samples; /* Actual MSAA layout used by the destination image. */ - enum intel_msaa_layout dst_layout; + enum isl_msaa_layout dst_layout; /* Type of the data to be read from the texture (one of * BRW_REGISTER_TYPE_{UD,D,F}). diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index f8ded37bbb8..e0550f3cc78 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -687,23 +687,18 @@ blorp_nir_retile_w_to_y(nir_builder *b, nir_ssa_def *pos) */ static inline nir_ssa_def * blorp_nir_encode_msaa(nir_builder *b, nir_ssa_def *pos, - unsigned num_samples, enum intel_msaa_layout layout) + unsigned num_samples, enum isl_msaa_layout layout) { assert(pos->num_components == 2 || pos->num_components == 3); switch (layout) { - case INTEL_MSAA_LAYOUT_NONE: + case ISL_MSAA_LAYOUT_NONE: assert(pos->num_components == 2); return pos; - case INTEL_MSAA_LAYOUT_CMS: - /* We can't compensate for compressed layout since at this point in the - * program we haven't read from the MCS buffer. - */ - unreachable("Bad layout in encode_msaa"); - case INTEL_MSAA_LAYOUT_UMS: + case ISL_MSAA_LAYOUT_ARRAY: /* No translation needed */ return pos; - case INTEL_MSAA_LAYOUT_IMS: { + case ISL_MSAA_LAYOUT_INTERLEAVED: { nir_ssa_def *x_in = nir_channel(b, pos, 0); nir_ssa_def *y_in = nir_channel(b, pos, 1); nir_ssa_def *s_in = pos->num_components == 2 ? nir_imm_int(b, 0) : @@ -790,24 +785,19 @@ blorp_nir_encode_msaa(nir_builder *b, nir_ssa_def *pos, */ static inline nir_ssa_def * blorp_nir_decode_msaa(nir_builder *b, nir_ssa_def *pos, - unsigned num_samples, enum intel_msaa_layout layout) + unsigned num_samples, enum isl_msaa_layout layout) { assert(pos->num_components == 2 || pos->num_components == 3); switch (layout) { - case INTEL_MSAA_LAYOUT_NONE: + case ISL_MSAA_LAYOUT_NONE: /* No translation necessary, and S should already be zero. */ assert(pos->num_components == 2); return pos; - case INTEL_MSAA_LAYOUT_CMS: - /* We can't compensate for compressed layout since at this point in the - * program we don't have access to the MCS buffer. - */ - unreachable("Bad layout in encode_msaa"); - case INTEL_MSAA_LAYOUT_UMS: + case ISL_MSAA_LAYOUT_ARRAY: /* No translation necessary. */ return pos; - case INTEL_MSAA_LAYOUT_IMS: { + case ISL_MSAA_LAYOUT_INTERLEAVED: { assert(pos->num_components == 2); nir_ssa_def *x_in = nir_channel(b, pos, 0); @@ -1335,13 +1325,13 @@ brw_blorp_build_nir_shader(struct brw_context *brw, } /* Make sure layout is consistent with sample count */ - assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) == + assert((key->tex_layout == ISL_MSAA_LAYOUT_NONE) == (key->tex_samples <= 1)); - assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) == + assert((key->rt_layout == ISL_MSAA_LAYOUT_NONE) == (key->rt_samples <= 1)); - assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) == + assert((key->src_layout == ISL_MSAA_LAYOUT_NONE) == (key->src_samples <= 1)); - assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) == + assert((key->dst_layout == ISL_MSAA_LAYOUT_NONE) == (key->dst_samples <= 1)); nir_builder b; @@ -1567,44 +1557,26 @@ brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform, } } - -/** - * Determine which MSAA layout the GPU pipeline should be configured for, - * based on the chip generation, the number of samples, and the true layout of - * the image in memory. - */ -inline intel_msaa_layout -compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples, - intel_msaa_layout true_layout) +static enum isl_msaa_layout +get_isl_msaa_layout(unsigned samples, enum intel_msaa_layout layout) { - if (num_samples <= 1) { - /* Layout is used to determine if ld2dms is needed for sampling. In - * single sampled case normal ld is enough avoiding also the need to - * fetch mcs. Therefore simply set the layout to none. - */ - if (brw->gen >= 9 && true_layout == INTEL_MSAA_LAYOUT_CMS) { - return INTEL_MSAA_LAYOUT_NONE; + if (samples > 1) { + switch (layout) { + case INTEL_MSAA_LAYOUT_NONE: + return ISL_MSAA_LAYOUT_NONE; + case INTEL_MSAA_LAYOUT_IMS: + return ISL_MSAA_LAYOUT_INTERLEAVED; + case INTEL_MSAA_LAYOUT_UMS: + case INTEL_MSAA_LAYOUT_CMS: + return ISL_MSAA_LAYOUT_ARRAY; + default: + unreachable("Invalid MSAA layout"); } - - /* When configuring the GPU for non-MSAA, we can still accommodate IMS - * format buffers, by transforming coordinates appropriately. - */ - assert(true_layout == INTEL_MSAA_LAYOUT_NONE || - true_layout == INTEL_MSAA_LAYOUT_IMS); - return INTEL_MSAA_LAYOUT_NONE; } else { - assert(true_layout != INTEL_MSAA_LAYOUT_NONE); - } - - /* Prior to Gen7, all MSAA surfaces use IMS layout. */ - if (brw->gen == 6) { - assert(true_layout == INTEL_MSAA_LAYOUT_IMS); + return ISL_MSAA_LAYOUT_NONE; } - - return true_layout; } - /** * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is @@ -1712,8 +1684,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw, * buffer). So if the destination is IMS, we'll have to map it as a * single-sampled texture and interleave the samples ourselves. */ - if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) + if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) { params.dst.surf.samples = 1; + params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_NONE; + } } if (params.src.surf.samples > 0 && params.dst.surf.samples > 1) { @@ -1775,31 +1749,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw, /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will * use to access the source and destination surfaces. */ - wm_prog_key.tex_layout = - compute_msaa_layout_for_pipeline(brw, params.src.surf.samples, - params.src.msaa_layout); - wm_prog_key.rt_layout = - compute_msaa_layout_for_pipeline(brw, params.dst.surf.samples, - params.dst.msaa_layout); + wm_prog_key.tex_layout = params.src.surf.msaa_layout; + wm_prog_key.rt_layout = params.dst.surf.msaa_layout; /* src_layout and dst_layout indicate the true MSAA layout used by src and * dst. */ - wm_prog_key.src_layout = src_mt->msaa_layout; - wm_prog_key.dst_layout = dst_mt->msaa_layout; - - /* On gen9+ compressed single sampled buffers carry the same layout type as - * multisampled. The difference is that they can be sampled using normal - * ld message and as render target behave just like non-compressed surface - * from compiler point of view. Therefore override the type in the program - * key. - */ - if (brw->gen >= 9 && params.src.surf.samples <= 1 && - src_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) - wm_prog_key.src_layout = INTEL_MSAA_LAYOUT_NONE; - if (brw->gen >= 9 && params.dst.surf.samples <= 1 && - dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) - wm_prog_key.dst_layout = INTEL_MSAA_LAYOUT_NONE; + wm_prog_key.src_layout = get_isl_msaa_layout(src_mt->num_samples, + src_mt->msaa_layout); + wm_prog_key.dst_layout = get_isl_msaa_layout(dst_mt->num_samples, + dst_mt->msaa_layout); /* Round floating point values to nearest integer to avoid "off by one texel" * kind of errors when blitting. |