diff options
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 14 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_cache.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 |
4 files changed, 16 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index c5cc8232616..17ae2bfe2b5 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -273,7 +273,7 @@ retry: /* We've smashed all state compared to what the normal 3D pipeline * rendering tracks for GL. */ - SET_DIRTY_ALL(brw); + SET_DIRTY64_ALL(brw); SET_DIRTY_ALL(cache); brw->no_depth_or_stencil = false; brw->ib.type = -1; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 13403f5a70c..ef68c53fd34 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -229,7 +229,7 @@ struct brw_state_flags { /** * State update flags signalled as the result of brw_tracked_state updates */ - GLuint brw; + uint64_t brw; /** * State update flags that used to be signalled by brw_state_cache.c * searches. @@ -283,6 +283,18 @@ typedef enum { /** + * Set all of the bits in a field of brw_state_flags. + */ +#define SET_DIRTY64_ALL(FIELD) \ + do { \ + /* ~0ULL == 0xffffffffffffffff, so make sure field is <= 64 bits */ \ + STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 8); \ + for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \ + brw->state.pipeline_dirty[pipeline].FIELD = ~(0ULL); \ + } while (false) + + +/** * Check one of the bits in a field of brw_state_flags. */ #define CHECK_DIRTY_BIT(FIELD, FLAG) \ diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index fcb7277bf27..19079c8b2cc 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -380,7 +380,7 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache) * any offsets leftover in brw_context will no longer be valid. */ SET_DIRTY_ALL(mesa); - SET_DIRTY_ALL(brw); + SET_DIRTY64_ALL(brw); SET_DIRTY_ALL(cache); intel_batchbuffer_flush(brw); } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 3022ab14e24..9d93431941c 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -391,7 +391,7 @@ void brw_init_state( struct brw_context *brw ) brw_upload_initial_gpu_state(brw); SET_DIRTY_ALL(mesa); - SET_DIRTY_ALL(brw); + SET_DIRTY64_ALL(brw); /* Make sure that brw->state.dirty.brw has enough bits to hold all possible * dirty flags. |