diff options
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 |
5 files changed, 10 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index 072ad5581e6..c55108a69fd 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -573,14 +573,14 @@ brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb, if (rb == NULL) continue; - if (fb->NumLayers > 0) { + if (fb->MaxNumLayers > 0) { unsigned layer_multiplier = (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? irb->mt->num_samples : 1; - assert(fb->NumLayers * layer_multiplier == - irb->mt->level[irb->mt_level].depth); - for (unsigned layer = 0; layer < fb->NumLayers; layer++) { + unsigned num_layers = + irb->mt->level[irb->mt_level].depth / layer_multiplier; + for (unsigned layer = 0; layer < num_layers; layer++) { if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear, layer * layer_multiplier)) { return false; diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 1cac996482d..fe68d9efcb9 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -181,9 +181,9 @@ brw_fast_clear_depth(struct gl_context *ctx) */ intel_batchbuffer_emit_mi_flush(brw); - if (fb->NumLayers > 0) { - assert(fb->NumLayers == depth_irb->mt->level[depth_irb->mt_level].depth); - for (unsigned layer = 0; layer < fb->NumLayers; layer++) { + if (fb->MaxNumLayers > 0) { + unsigned num_layers = depth_irb->mt->level[depth_irb->mt_level].depth; + for (unsigned layer = 0; layer < num_layers; layer++) { intel_hiz_exec(brw, mt, depth_irb->mt_level, layer, GEN6_HIZ_OP_DEPTH_CLEAR); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index acb1a40e632..e83763137d7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -700,7 +700,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], - ctx->DrawBuffer->NumLayers > 0, i); + ctx->DrawBuffer->MaxNumLayers > 0, i); } else { brw->vtbl.update_null_renderbuffer_surface(brw, i); } diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index 37a39b83fb7..6cec0ff21ac 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -121,7 +121,7 @@ upload_clip_state(struct brw_context *brw) dw2); OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT | U_FIXED(255.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT | - (fb->NumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX)); + (fb->MaxNumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX)); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 42519494d3c..8fb0eec7765 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -81,7 +81,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, break; } - if (fb->NumLayers > 0 || !irb) { + if (fb->MaxNumLayers > 0 || !irb) { min_array_element = 0; } else if (irb->mt->num_samples > 1) { /* Convert physical layer to logical layer. */ |