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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h9
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c3
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c130
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c143
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h17
5 files changed, 35 insertions, 267 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index efed5a626d0..08106c00770 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -354,12 +354,6 @@
#define GEN7_SURFACE_MOCS_SHIFT 16
#define GEN7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)
-#define GEN9_SURFACE_TRMODE_SHIFT 18
-#define GEN9_SURFACE_TRMODE_MASK INTEL_MASK(19, 18)
-#define GEN9_SURFACE_TRMODE_NONE 0
-#define GEN9_SURFACE_TRMODE_TILEYF 1
-#define GEN9_SURFACE_TRMODE_TILEYS 2
-
#define GEN9_SURFACE_MIP_TAIL_START_LOD_SHIFT 8
#define GEN9_SURFACE_MIP_TAIL_START_LOD_MASK INTEL_MASK(11, 8)
@@ -1620,9 +1614,6 @@ enum brw_pixel_shader_coverage_mask_mode {
#define BR13_16161616 (0x4 << 24)
#define BR13_32323232 (0x5 << 24)
-#define XY_FAST_SRC_TRMODE_YF (1 << 31)
-#define XY_FAST_DST_TRMODE_YF (1 << 30)
-
/* Pipeline Statistics Counter Registers */
#define IA_VERTICES_COUNT 0x2310
#define IA_PRIMITIVES_COUNT 0x2318
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1cf6b04e05f..83c1810e8db 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -177,7 +177,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t tile_mask_x = 0, tile_mask_y = 0;
if (depth_mt) {
- intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
+ intel_get_tile_masks(depth_mt->tiling,
depth_mt->cpp,
&tile_mask_x, &tile_mask_y);
assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
@@ -194,7 +194,6 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
} else {
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
intel_get_tile_masks(stencil_mt->tiling,
- stencil_mt->tr_mode,
stencil_mt->cpp,
&stencil_tile_mask_x,
&stencil_tile_mask_y);
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 8a528e088a4..bfa8afaa698 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -40,74 +40,6 @@
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
static unsigned int
-tr_mode_horizontal_texture_alignment(const struct intel_mipmap_tree *mt)
-{
- unsigned ret_align, divisor, multiplier_ys;
-
- /* Values in below tables specifiy the horizontal alignment requirement
- * in elements for TRMODE_YF surface. An element is defined as a pixel in
- * uncompressed surface formats, and as a compression block in compressed
- * surface formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
- * element is a sample.
- */
- const unsigned align_1d_yf[] = {4096, 2048, 1024, 512, 256};
- const unsigned align_2d_yf[] = {64, 64, 32, 32, 16};
- const unsigned align_3d_yf[] = {16, 8, 8, 8, 4};
-
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);
-
- /* Alignment computations below assume a power of 2 cpp. */
- assert (mt->cpp >= 1 && mt->cpp <= 16 && _mesa_is_pow_two(mt->cpp));
- /* Compute array index. */
- const int i = ffs(mt->cpp) - 1;
-
- switch(mt->target) {
- case GL_TEXTURE_1D:
- case GL_TEXTURE_1D_ARRAY:
- ret_align = align_1d_yf[i];
- multiplier_ys = 16;
- break;
- case GL_TEXTURE_2D:
- case GL_TEXTURE_RECTANGLE:
- case GL_TEXTURE_2D_ARRAY:
- case GL_TEXTURE_CUBE_MAP:
- case GL_TEXTURE_CUBE_MAP_ARRAY:
- case GL_TEXTURE_2D_MULTISAMPLE:
- case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
- ret_align = align_2d_yf[i];
- multiplier_ys = 4;
- break;
- case GL_TEXTURE_3D:
- ret_align = align_3d_yf[i];
- multiplier_ys = 4;
- break;
- default:
- unreachable("not reached");
- }
-
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)
- ret_align *= multiplier_ys;
-
- assert(_mesa_is_pow_two(mt->num_samples));
-
- switch (mt->num_samples) {
- case 2:
- case 4:
- divisor = 2;
- break;
- case 8:
- case 16:
- divisor = 4;
- break;
- default:
- divisor = 1;
- break;
- }
- return ret_align / divisor;
-}
-
-
-static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
@@ -141,63 +73,6 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
}
static unsigned int
-tr_mode_vertical_texture_alignment(const struct intel_mipmap_tree *mt)
-{
- unsigned ret_align, divisor, multiplier_ys;
-
- /* Vertical alignment tables for TRMODE_YF */
- const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
- const unsigned align_3d_yf[] = {16, 16, 16, 8, 8};
-
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);
-
- /* Alignment computations below assume a power of 2 cpp. */
- assert (mt->cpp >= 1 && mt->cpp <= 16 && _mesa_is_pow_two(mt->cpp)) ;
- /* Compute array index. */
- const int i = ffs(mt->cpp) - 1;
-
- switch(mt->target) {
- case GL_TEXTURE_2D:
- case GL_TEXTURE_RECTANGLE:
- case GL_TEXTURE_2D_ARRAY:
- case GL_TEXTURE_CUBE_MAP:
- case GL_TEXTURE_CUBE_MAP_ARRAY:
- case GL_TEXTURE_2D_MULTISAMPLE:
- case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
- ret_align = align_2d_yf[i];
- multiplier_ys = 4;
- break;
- case GL_TEXTURE_3D:
- ret_align = align_3d_yf[i];
- multiplier_ys = 2;
- break;
- case GL_TEXTURE_1D:
- case GL_TEXTURE_1D_ARRAY:
- default:
- unreachable("Unexpected miptree target");
- }
-
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)
- ret_align *= multiplier_ys;
-
- assert(_mesa_is_pow_two(mt->num_samples));
-
- switch (mt->num_samples) {
- case 4:
- case 8:
- divisor = 2;
- break;
- case 16:
- divisor = 4;
- break;
- default:
- divisor = 1;
- break;
- }
- return ret_align / divisor;
-}
-
-static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
@@ -753,9 +628,6 @@ intel_miptree_set_alignment(struct brw_context *brw,
} else if (mt->format == MESA_FORMAT_S_UINT8) {
mt->halign = 8;
mt->valign = brw->gen >= 7 ? 8 : 4;
- } else if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
- mt->halign = tr_mode_horizontal_texture_alignment(mt);
- mt->valign = tr_mode_vertical_texture_alignment(mt);
} else {
mt->halign =
intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
@@ -768,8 +640,6 @@ brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
- mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
-
intel_miptree_set_alignment(brw, mt, layout_flags);
intel_miptree_set_total_width_height(brw, mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3295175d0b4..467ada5079b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -576,34 +576,6 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
}
}
-/* This function computes Yf/Ys tiled bo size, alignment and pitch. */
-static unsigned long
-intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt, unsigned *alignment,
- unsigned long *pitch)
-{
- uint32_t tile_width, tile_height;
- unsigned long stride, size, aligned_y;
-
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);
- intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp,
- &tile_width, &tile_height);
-
- aligned_y = ALIGN(mt->total_height, tile_height);
- stride = mt->total_width * mt->cpp;
- stride = ALIGN(stride, tile_width);
- size = stride * aligned_y;
-
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YF) {
- assert(size % 4096 == 0);
- *alignment = 4096;
- } else {
- assert(size % (64 * 1024) == 0);
- *alignment = 64 * 1024;
- }
- *pitch = stride;
- return size;
-}
-
static struct intel_mipmap_tree *
miptree_create(struct brw_context *brw,
GLenum target,
@@ -642,27 +614,18 @@ miptree_create(struct brw_context *brw,
unsigned long pitch;
mt->etc_format = etc_format;
- if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
- unsigned alignment = 0;
- unsigned long size;
- size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);
- assert(size);
- mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
- size, alignment);
+ if (format == MESA_FORMAT_S_UINT8) {
+ /* Align to size of W tile, 64x64. */
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ ALIGN(mt->total_width, 64),
+ ALIGN(mt->total_height, 64),
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
} else {
- if (format == MESA_FORMAT_S_UINT8) {
- /* Align to size of W tile, 64x64. */
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
- ALIGN(mt->total_width, 64),
- ALIGN(mt->total_height, 64),
- mt->cpp, &mt->tiling, &pitch,
- alloc_flags);
- } else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
- mt->total_width, mt->total_height,
- mt->cpp, &mt->tiling, &pitch,
- alloc_flags);
- }
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->total_width, mt->total_height,
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
}
mt->pitch = pitch;
@@ -1148,53 +1111,24 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
* and tile_h is set to 1.
*/
void
-intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+intel_get_tile_dims(uint32_t tiling, uint32_t cpp,
uint32_t *tile_w, uint32_t *tile_h)
{
- if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) {
- switch (tiling) {
- case I915_TILING_X:
- *tile_w = 512;
- *tile_h = 8;
- break;
- case I915_TILING_Y:
- *tile_w = 128;
- *tile_h = 32;
- break;
- case I915_TILING_NONE:
- *tile_w = cpp;
- *tile_h = 1;
- break;
- default:
- unreachable("not reached");
- }
- } else {
- uint32_t aspect_ratio = 1;
- assert(_mesa_is_pow_two(cpp));
-
- switch (cpp) {
- case 1:
- *tile_h = 64;
- break;
- case 2:
- case 4:
- *tile_h = 32;
- break;
- case 8:
- case 16:
- *tile_h = 16;
- break;
- default:
- unreachable("not reached");
- }
-
- if (cpp == 2 || cpp == 8)
- aspect_ratio = 2;
-
- if (tr_mode == INTEL_MIPTREE_TRMODE_YS)
- *tile_h *= 4;
-
- *tile_w = *tile_h * aspect_ratio * cpp;
+ switch (tiling) {
+ case I915_TILING_X:
+ *tile_w = 512;
+ *tile_h = 8;
+ break;
+ case I915_TILING_Y:
+ *tile_w = 128;
+ *tile_h = 32;
+ break;
+ case I915_TILING_NONE:
+ *tile_w = cpp;
+ *tile_h = 1;
+ break;
+ default:
+ unreachable("not reached");
}
}
@@ -1205,12 +1139,12 @@ intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
* untiled, the masks are set to 0.
*/
void
-intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+intel_get_tile_masks(uint32_t tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y)
{
uint32_t tile_w_bytes, tile_h;
- intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h);
+ intel_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
*mask_x = tile_w_bytes / cpp - 1;
*mask_y = tile_h - 1;
@@ -1264,7 +1198,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, &mask_x, &mask_y);
+ intel_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
@@ -3072,11 +3006,9 @@ use_intel_mipree_map_blit(struct brw_context *brw,
{
if (brw->has_llc &&
/* It's probably not worth swapping to the blit ring because of
- * all the overhead involved. But, we must use blitter for the
- * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
+ * all the overhead involved.
*/
- (!(mode & GL_MAP_WRITE_BIT) ||
- mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) &&
+ !(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->tiling == I915_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
@@ -3151,8 +3083,6 @@ intel_miptree_map(struct brw_context *brw,
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
- /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
- assert(mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE);
intel_miptree_map_gtt(brw, mt, map, level, slice);
}
@@ -3267,16 +3197,7 @@ intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
case I915_TILING_X:
return ISL_TILING_X;
case I915_TILING_Y:
- switch (mt->tr_mode) {
- case INTEL_MIPTREE_TRMODE_NONE:
return ISL_TILING_Y0;
- case INTEL_MIPTREE_TRMODE_YF:
- return ISL_TILING_Yf;
- case INTEL_MIPTREE_TRMODE_YS:
- return ISL_TILING_Ys;
- default:
- unreachable("Invalid tiled resource mode");
- }
default:
unreachable("Invalid tiling mode");
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 27bcdfbe334..c03233a3d84 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -333,13 +333,6 @@ struct intel_miptree_hiz_buffer
struct intel_mipmap_tree *mt;
};
-/* Tile resource modes */
-enum intel_miptree_tr_mode {
- INTEL_MIPTREE_TRMODE_NONE,
- INTEL_MIPTREE_TRMODE_YF,
- INTEL_MIPTREE_TRMODE_YS
-};
-
struct intel_mipmap_tree
{
/**
@@ -374,12 +367,6 @@ struct intel_mipmap_tree
uint32_t tiling;
/**
- * @see RENDER_SURFACE_STATE.TiledResourceMode
- * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
- */
- enum intel_miptree_tr_mode tr_mode;
-
- /**
* @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
*
* @see RENDER_SURFACE_STATE.SurfaceType
@@ -806,11 +793,11 @@ intel_get_image_dims(struct gl_texture_image *image,
int *width, int *height, int *depth);
void
-intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+intel_get_tile_masks(uint32_t tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y);
void
-intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+intel_get_tile_dims(uint32_t tiling, uint32_t cpp,
uint32_t *tile_w, uint32_t *tile_h);
uint32_t
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 10:53:20 +0000