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-rw-r--r--src/mesa/drivers/dri/intel/intel_chipset.h13
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c9
2 files changed, 20 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index eefb430f0b3..424c70ce2f1 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -86,6 +86,12 @@
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
+#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */
+
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
devid == PCI_CHIP_I945_GM || \
@@ -154,8 +160,11 @@
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
IS_HASWELL(devid))
-#define IS_HSW_GT1(devid) 0
-#define IS_HSW_GT2(devid) 0
+#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
+ devid == PCI_CHIP_HASWELL_M_GT1)
+#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
+ devid == PCI_CHIP_HASWELL_M_GT2 || \
+ devid == PCI_CHIP_HASWELL_M_ULT_GT2)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid))
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 1aa2e9a40ec..ff2b7feec8d 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -185,6 +185,15 @@ intelGetString(struct gl_context * ctx, GLenum name)
case PCI_CHIP_IVYBRIDGE_S_GT1:
chipset = "Intel(R) Ivybridge Server";
break;
+ case PCI_CHIP_HASWELL_GT1:
+ case PCI_CHIP_HASWELL_GT2:
+ chipset = "Intel(R) Haswell Desktop";
+ break;
+ case PCI_CHIP_HASWELL_M_GT1:
+ case PCI_CHIP_HASWELL_M_GT2:
+ case PCI_CHIP_HASWELL_M_ULT_GT2:
+ chipset = "Intel(R) Haswell Mobile";
+ break;
default:
chipset = "Unknown Intel Chipset";
break;