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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index dc38acea21b..0fc24a7ede9 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -38,14 +38,6 @@
/* 3D state:
*/
-#define PIPE_CONTROL_NOWRITE 0x00
-#define PIPE_CONTROL_WRITEIMMEDIATE 0x01
-#define PIPE_CONTROL_WRITEDEPTH 0x02
-#define PIPE_CONTROL_WRITETIMESTAMP 0x03
-
-#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
-#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01
-
#define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */
/* DW0 */
# define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10
@@ -1919,8 +1911,6 @@ enum brw_wm_barycentric_interp_mode {
/* DW2: start address */
/* DW3: end address. */
-#define CMD_PIPE_CONTROL 0x7a00
-
#define CMD_MI_FLUSH 0x0200
#define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))