diff options
Diffstat (limited to 'src/mesa/drivers/dri/r600')
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_cmdbuf.c | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_texstate.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_assembler.c | 13 |
3 files changed, 25 insertions, 18 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 3cfe03a45f7..d27a3245a39 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -254,7 +254,7 @@ static int r600_cs_process_relocs(struct radeon_cs *cs, relocs = (struct r600_cs_reloc_legacy *)cs->relocs; restart: for (i = 0; i < cs->crelocs; i++) { - uint32_t soffset, eoffset, asicoffset; + uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); @@ -262,24 +262,12 @@ restart: goto restart; } if (r) { - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + fprintf(stderr, "invalid bo(%p) [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); return r; } - asicoffset = soffset; for (j = 0; j < relocs[i].cindices; j++) { - if (asicoffset >= eoffset) { - /* radeon_bo_debug(relocs[i].base.bo, 12); */ - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); - fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", - relocs[i].base.bo, - cs->packets[relocs[i].indices[j]], - eoffset); - exit(0); - return -EINVAL; - } /* pkt3 nop header in ib chunk */ cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; /* reloc index in ib chunk */ @@ -287,7 +275,7 @@ restart: } /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ - reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw] = soffset; reloc_chunk[offset_dw + 3] = 0; offset_dw += 4; diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 7d7e77d355b..ba1371bf95a 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -764,7 +764,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t = radeon_tex_obj(tObj); - uint32_t pitch_val, size; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + const struct gl_texture_image *firstImage; + uint32_t pitch_val, size, row_align, bpp; if (!tObj) return; @@ -774,7 +776,13 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - size = pitch;//h * w * (depth / 8); + bpp = depth / 8; + if (bpp == 3) + bpp = 4; + + firstImage = t->base.Image[0][firstlevel]; + row_align = rmesa->radeon.texture_row_align - 1; + size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index ed597c027b5..e07f9baa05b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1307,8 +1307,10 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) case PROGRAM_INPUT: switch (pILInst->SrcReg[0].Index) { + case FRAG_ATTRIB_WPOS: case FRAG_ATTRIB_COL0: case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_FOGC: case FRAG_ATTRIB_TEX0: case FRAG_ATTRIB_TEX1: case FRAG_ATTRIB_TEX2: @@ -1321,7 +1323,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; pAsm->S[0].src.rtype = SRC_REG_INPUT; - break; + break; + case FRAG_ATTRIB_FACE: + fprintf(stderr, "FRAG_ATTRIB_FACE unsupported\n"); + break; + case FRAG_ATTRIB_PNTC: + fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n"); + break; + case FRAG_ATTRIB_VAR0: + fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n"); + break; } break; } |