diff options
Diffstat (limited to 'src/mesa/drivers/dri/r600')
| -rw-r--r-- | src/mesa/drivers/dri/r600/evergreen_chip.c | 28 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_chip.c | 27 |
2 files changed, 46 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c index f02032b8ce8..1050c776bf7 100644 --- a/src/mesa/drivers/dri/r600/evergreen_chip.c +++ b/src/mesa/drivers/dri/r600/evergreen_chip.c @@ -865,7 +865,7 @@ static void evergreenSetDepthTarget(context_t *context) { EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) @@ -879,13 +879,22 @@ static void evergreenSetDepthTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift, EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask); - SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1, + SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1, EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift, EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask); - evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1; + evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1; if(4 == rrb->cpp) { @@ -1052,7 +1061,7 @@ static void evergreenSetRenderTarget(context_t *context, int id) EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1; struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -1067,13 +1076,22 @@ static void evergreenSetRenderTarget(context_t *context, int id) /* pitch */ nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1, EG_CB_COLOR0_PITCH__TILE_MAX_shift, EG_CB_COLOR0_PITCH__TILE_MAX_mask); /* slice */ SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All, - ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + ( (nPitchInPixel * height)/64 )-1, EG_CB_COLOR0_SLICE__TILE_MAX_shift, EG_CB_COLOR0_SLICE__TILE_MAX_mask); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 51dad61297e..3bb194eb6d6 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -270,7 +270,7 @@ static void r700SetRenderTarget(context_t *context, int id) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM; struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -283,9 +283,19 @@ static void r700SetRenderTarget(context_t *context, int id) r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256; nPitchInPixel = rrb->pitch/rrb->cpp; + + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, @@ -544,7 +554,7 @@ static void r700SetDepthTarget(context_t *context) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) @@ -560,9 +570,18 @@ static void r700SetDepthTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ if(4 == rrb->cpp) |