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Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_chip.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c125
1 files changed, 125 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 16f1a3df366..37bff56f5a9 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -49,6 +49,8 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
unsigned int i;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
+
for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
radeonTexObj *t = r700->textures[i];
if (t) {
@@ -93,6 +95,7 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
unsigned int i;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
radeonTexObj *t = r700->textures[i];
@@ -115,6 +118,7 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
unsigned int i;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
radeonTexObj *t = r700->textures[i];
@@ -141,6 +145,7 @@ static void r700SetupVTXConstants(GLcontext * ctx,
context_t *context = R700_CONTEXT(ctx);
struct radeon_aos * paos = (struct radeon_aos *)pAos;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
unsigned int uSQ_VTX_CONSTANT_WORD0_0;
unsigned int uSQ_VTX_CONSTANT_WORD1_0;
@@ -205,6 +210,7 @@ void r700SetupStreams(GLcontext *ctx)
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
unsigned int i, j = 0;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
R600_STATECHANGE(context, vtx);
@@ -229,6 +235,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
= (struct r700_vertex_program *)ctx->VertexProgram._Current;
unsigned int i, j = 0;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (context->radeon.tcl.aos_count == 0)
return;
@@ -258,12 +265,100 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
}
}
+static void r700SetRenderTarget(context_t *context, int id)
+{
+ R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+ struct radeon_renderbuffer *rrb;
+ unsigned int nPitchInPixel;
+
+ rrb = radeon_get_colorbuffer(&context->radeon);
+ if (!rrb || !rrb->bo) {
+ return;
+ }
+
+ R600_STATECHANGE(context, cb_target);
+
+ /* color buffer */
+ r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
+
+ nPitchInPixel = rrb->pitch/rrb->cpp;
+ SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
+ PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
+ SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
+ r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
+ CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
+ if(4 == rrb->cpp)
+ {
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
+ CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
+ }
+ else
+ {
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
+ CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
+ COMP_SWAP_shift, COMP_SWAP_mask);
+ }
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
+ SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
+ SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
+
+ r700->render_target[id].enabled = GL_TRUE;
+}
+
+static void r700SetDepthTarget(context_t *context)
+{
+ R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+ struct radeon_renderbuffer *rrb;
+ unsigned int nPitchInPixel;
+
+ rrb = radeon_get_depthbuffer(&context->radeon);
+ if (!rrb)
+ return;
+
+ R600_STATECHANGE(context, db_target);
+
+ /* depth buf */
+ r700->DB_DEPTH_SIZE.u32All = 0;
+ r700->DB_DEPTH_BASE.u32All = 0;
+ r700->DB_DEPTH_INFO.u32All = 0;
+ r700->DB_DEPTH_VIEW.u32All = 0;
+
+ nPitchInPixel = rrb->pitch/rrb->cpp;
+
+ SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
+ PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
+ SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
+ SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
+
+ if(4 == rrb->cpp)
+ {
+ SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
+ DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
+ }
+ else
+ {
+ SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
+ DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
+ }
+ SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
+ DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
+ /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
+}
+
static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_renderbuffer *rrb;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
rrb = radeon_get_depthbuffer(&context->radeon);
if (!rrb || !rrb->bo) {
@@ -271,6 +366,8 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
return;
}
+ r700SetDepthTarget(context);
+
BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
@@ -303,6 +400,7 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
struct radeon_renderbuffer *rrb;
BATCH_LOCALS(&context->radeon);
int id = 0;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
rrb = radeon_get_colorbuffer(&context->radeon);
if (!rrb || !rrb->bo) {
@@ -310,6 +408,8 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
return;
}
+ r700SetRenderTarget(context, 0);
+
if (id > R700_MAX_RENDER_TARGETS)
return;
@@ -352,6 +452,7 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
@@ -385,6 +486,7 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
@@ -416,6 +518,7 @@ static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
/* XXX fixme
* R6xx chips require a FS be emitted, even if it's not used.
@@ -457,6 +560,7 @@ static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
int id = 0;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (id > R700_MAX_VIEWPORTS)
return;
@@ -489,6 +593,7 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(34);
R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
@@ -526,6 +631,7 @@ static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
int i;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
for (i = 0; i < R700_MAX_UCP; i++) {
if (r700->ucp[i].enabled) {
@@ -547,6 +653,7 @@ static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
unsigned int ui;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
@@ -620,6 +727,7 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(41);
@@ -665,6 +773,7 @@ static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(9);
R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
@@ -679,6 +788,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(23);
R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
@@ -720,6 +830,7 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
BEGIN_BATCH_NO_AUTOSTATE(11);
@@ -766,6 +877,7 @@ static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
unsigned int ui;
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
BEGIN_BATCH_NO_AUTOSTATE(3);
@@ -796,6 +908,7 @@ static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(6);
R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
@@ -850,6 +963,7 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(12);
R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
@@ -881,6 +995,7 @@ static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(22);
R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
@@ -913,6 +1028,7 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
BEGIN_BATCH_NO_AUTOSTATE(15);
R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
@@ -969,6 +1085,7 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
int i;
BATCH_LOCALS(&context->radeon);
+ radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (r700->vs.num_consts == 0)
return;
@@ -999,6 +1116,7 @@ static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
count += 11;
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1019,6 +1137,7 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
count += 3;
}
}
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1034,6 +1153,7 @@ static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
if (r700->ucp[i].enabled)
count += 6;
}
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1045,6 +1165,7 @@ static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
if (count)
count += 6;
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1059,6 +1180,7 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
if (t)
count++;
}
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count * 31;
}
@@ -1070,6 +1192,7 @@ static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
if (count)
count += 2;
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1082,6 +1205,7 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
if (count)
count += 2;
+ radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
@@ -1101,6 +1225,7 @@ do { \
void r600InitAtoms(context_t *context)
{
+ radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
/* Setup the atom linked list */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 03:12:19 +0000