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-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen6_clip_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 662c975edc1..fd6954b359e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -701,7 +701,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->Layered, i);
+ ctx->DrawBuffer->NumLayers > 0, i);
} else {
brw->vtbl.update_null_renderbuffer_surface(brw, i);
}
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 03d0f9057c1..37a39b83fb7 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -121,7 +121,7 @@ upload_clip_state(struct brw_context *brw)
dw2);
OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
U_FIXED(255.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT |
- (fb->Layered ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX));
+ (fb->NumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX));
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 3f3833e98e6..42519494d3c 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -81,7 +81,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
- if (fb->Layered || !irb) {
+ if (fb->NumLayers > 0 || !irb) {
min_array_element = 0;
} else if (irb->mt->num_samples > 1) {
/* Convert physical layer to logical layer. */