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-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c14
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c8
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_surface_state.c14
4 files changed, 24 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7b83ff5253c..2e6780be772 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -205,11 +205,11 @@ static void prepare_depthbuffer(struct brw_context *brw)
struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (drb)
- brw_add_validated_bo(brw, drb->region->buffer);
+ brw_add_validated_bo(brw, drb->region->bo);
if (drb && drb->hiz_region)
- brw_add_validated_bo(brw, drb->hiz_region->buffer);
+ brw_add_validated_bo(brw, drb->hiz_region->bo);
if (srb)
- brw_add_validated_bo(brw, srb->region->buffer);
+ brw_add_validated_bo(brw, srb->region->bo);
}
static void emit_depthbuffer(struct brw_context *brw)
@@ -348,7 +348,7 @@ static void emit_depthbuffer(struct brw_context *brw)
(BRW_TILEWALK_YMAJOR << 26) |
((region->tiling != I915_TILING_NONE) << 27) |
(BRW_SURFACE_2D << 29));
- OUT_RELOC(region->buffer,
+ OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
@@ -381,7 +381,7 @@ static void emit_depthbuffer(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
- OUT_RELOC(hiz_region->buffer,
+ OUT_RELOC(hiz_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
@@ -398,7 +398,7 @@ static void emit_depthbuffer(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
- OUT_RELOC(stencil_irb->region->buffer,
+ OUT_RELOC(stencil_irb->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 5be5c162490..aae1eed83f2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -244,7 +244,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
sampler->sRGBDecode) <<
BRW_SURFACE_FORMAT_SHIFT));
- surf[1] = intelObj->mt->region->buffer->offset; /* reloc */
+ surf[1] = intelObj->mt->region->bo->offset; /* reloc */
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(firstImage->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -261,7 +261,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[surf_index] + 4,
- intelObj->mt->region->buffer, 0,
+ intelObj->mt->region->bo, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
}
@@ -488,7 +488,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/* reloc */
surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
- region->buffer->offset);
+ region->bo->offset);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -531,8 +531,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[unit] + 4,
- region->buffer,
- surf[1] - region->buffer->offset,
+ region->bo,
+ surf[1] - region->bo->offset,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
}
@@ -550,7 +550,7 @@ prepare_wm_surfaces(struct brw_context *brw)
struct intel_region *region = irb ? irb->region : NULL;
if (region)
- brw_add_validated_bo(brw, region->buffer);
+ brw_add_validated_bo(brw, region->bo);
nr_surfaces = SURF_INDEX_DRAW(i) + 1;
}
@@ -566,7 +566,7 @@ prepare_wm_surfaces(struct brw_context *brw)
struct gl_texture_object *tObj = texUnit->_Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
- brw_add_validated_bo(brw, intelObj->mt->region->buffer);
+ brw_add_validated_bo(brw, intelObj->mt->region->bo);
nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 9eb75e2a76d..e16064115f6 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -65,9 +65,9 @@ static void prepare_depthbuffer(struct brw_context *brw)
struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (drb)
- brw_add_validated_bo(brw, drb->region->buffer);
+ brw_add_validated_bo(brw, drb->region->bo);
if (srb)
- brw_add_validated_bo(brw, srb->region->buffer);
+ brw_add_validated_bo(brw, srb->region->bo);
}
static void emit_depthbuffer(struct brw_context *brw)
@@ -128,7 +128,7 @@ static void emit_depthbuffer(struct brw_context *brw)
((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) |
((ctx->Depth.Mask != 0) << 28) |
(BRW_SURFACE_2D << 29));
- OUT_RELOC(region->buffer,
+ OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
@@ -155,7 +155,7 @@ static void emit_depthbuffer(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(srb->region->pitch * srb->region->cpp - 1);
- OUT_RELOC(srb->region->buffer,
+ OUT_RELOC(srb->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 4add1a69f02..b148c53deea 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -95,7 +95,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
* - render_cache_read_write (exists on gen6 but ignored here)
*/
- surf->ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
+ surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */
surf->ss2.width = firstImage->Width - 1;
surf->ss2.height = firstImage->Height - 1;
@@ -118,7 +118,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[surf_index] +
offsetof(struct gen7_surface_state, ss1),
- intelObj->mt->region->buffer, 0,
+ intelObj->mt->region->bo, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
}
@@ -275,7 +275,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
surf->ss0.surface_type = BRW_SURFACE_2D;
/* reloc */
surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
- surf->ss1.base_addr += region->buffer->offset; /* reloc */
+ surf->ss1.base_addr += region->bo->offset; /* reloc */
assert(brw->has_surface_tile_offset);
/* Note that the low bits of these fields are missing, so
@@ -294,8 +294,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[unit] +
offsetof(struct gen7_surface_state, ss1),
- region->buffer,
- surf->ss1.base_addr - region->buffer->offset,
+ region->bo,
+ surf->ss1.base_addr - region->bo->offset,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
}
@@ -314,7 +314,7 @@ prepare_wm_surfaces(struct brw_context *brw)
struct intel_region *region = irb ? irb->region : NULL;
if (region)
- brw_add_validated_bo(brw, region->buffer);
+ brw_add_validated_bo(brw, region->bo);
nr_surfaces = SURF_INDEX_DRAW(i) + 1;
}
}
@@ -330,7 +330,7 @@ prepare_wm_surfaces(struct brw_context *brw)
struct intel_texture_object *intelObj = intel_texture_object(tObj);
if (texUnit->_ReallyEnabled) {
- brw_add_validated_bo(brw, intelObj->mt->region->buffer);
+ brw_add_validated_bo(brw, intelObj->mt->region->bo);
nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 10:00:47 +0000