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-rw-r--r--src/mesa/drivers/dri/i965/brw_curbe.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c14
-rw-r--r--src/mesa/drivers/dri/i965/brw_queryobj.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_batch.c4
7 files changed, 19 insertions, 20 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index aadcfbe2dac..190310afbb0 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -340,7 +340,7 @@ static void emit_constant_buffer(struct brw_context *brw)
struct intel_context *intel = &brw->intel;
GLuint sz = brw->curbe.total_size;
- BEGIN_BATCH(2, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2);
if (sz == 0) {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2));
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index f99d607d86e..8d80c8bcfc8 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -157,7 +157,7 @@ static void brw_emit_prim(struct brw_context *brw,
}
if (prim_packet.verts_per_instance) {
intel_batchbuffer_data( brw->intel.batch, &prim_packet,
- sizeof(prim_packet), LOOP_CLIPRECTS);
+ sizeof(prim_packet));
}
if (intel->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(intel->batch);
@@ -353,8 +353,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
* an upper bound of how much we might emit in a single
* brw_try_draw_prims().
*/
- intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4,
- LOOP_CLIPRECTS);
+ intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4);
hw_prim = brw_set_prim(brw, prim[i].mode);
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 2c9902c90f0..c773b71507c 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -494,7 +494,7 @@ static void brw_emit_vertices(struct brw_context *brw)
* a VE loads from them.
*/
if (brw->vb.nr_enabled == 0) {
- BEGIN_BATCH(3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(3);
OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
BRW_VE0_VALID |
@@ -514,7 +514,7 @@ static void brw_emit_vertices(struct brw_context *brw)
* are interleaved or from the same VBO. TBD if this makes a
* performance difference.
*/
- BEGIN_BATCH(1 + brw->vb.nr_enabled * 4, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(1 + brw->vb.nr_enabled * 4);
OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
((1 + brw->vb.nr_enabled * 4) - 2));
@@ -537,7 +537,7 @@ static void brw_emit_vertices(struct brw_context *brw)
}
ADVANCE_BATCH();
- BEGIN_BATCH(1 + brw->vb.nr_enabled * 2, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(1 + brw->vb.nr_enabled * 2);
OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2));
for (i = 0; i < brw->vb.nr_enabled; i++) {
struct brw_vertex_element *input = brw->vb.enabled[i];
@@ -704,7 +704,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
ib.header.bits.index_format = get_index_type(index_buffer->type);
ib.header.bits.cut_index_enable = 0;
- BEGIN_BATCH(4, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(4);
OUT_BATCH( ib.header.dword );
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 2155feec845..1bd3979f9b0 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -81,7 +81,7 @@ static void upload_drawing_rect(struct brw_context *brw)
if (!intel->constant_cliprect)
return;
- BEGIN_BATCH(4, NO_LOOP_CLIPRECTS);
+ BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
OUT_BATCH(0); /* xmin, ymin */
OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
@@ -116,7 +116,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- BEGIN_BATCH(6, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(6);
OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
if (brw->vs.bind_bo != NULL)
OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */
@@ -150,7 +150,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
{
struct intel_context *intel = &brw->intel;
- BEGIN_BATCH(7, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(7);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
@@ -215,7 +215,7 @@ static void emit_depthbuffer(struct brw_context *brw)
unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5;
if (region == NULL) {
- BEGIN_BATCH(len, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(len);
OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
(BRW_SURFACE_NULL << 29));
@@ -247,7 +247,7 @@ static void emit_depthbuffer(struct brw_context *brw)
assert(region->tiling != I915_TILING_X);
- BEGIN_BATCH(len, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(len);
OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
@@ -513,7 +513,7 @@ static void upload_state_base_address( struct brw_context *brw )
* batchbuffer, so we can emit relocations inline.
*/
if (intel->is_ironlake) {
- BEGIN_BATCH(8, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
OUT_BATCH(1); /* Surface state base address */
@@ -524,7 +524,7 @@ static void upload_state_base_address( struct brw_context *brw )
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(6, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
OUT_BATCH(1); /* Surface state base address */
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index a195bc32b07..5399a742449 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -188,7 +188,7 @@ brw_emit_query_begin(struct brw_context *brw)
if (brw->query.active || is_empty_list(&brw->query.active_head))
return;
- BEGIN_BATCH(4, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT);
@@ -227,7 +227,7 @@ brw_emit_query_end(struct brw_context *brw)
if (!brw->query.active)
return;
- BEGIN_BATCH(4, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT);
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 14d5319796a..9c9d145c4b6 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -151,7 +151,7 @@ void brw_state_cache_bo_delete(struct brw_cache *cache, dri_bo *bo);
/***********************************************************************
* brw_state_batch.c
*/
-#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)), IGNORE_CLIPRECTS)
+#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)))
#define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) )
GLboolean brw_cached_batch_struct( struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 7821898cf9b..ed8120d617f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -48,7 +48,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
struct header *newheader = (struct header *)data;
if (brw->emit_state_always) {
- intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS);
+ intel_batchbuffer_data(brw->intel.batch, data, sz);
return GL_TRUE;
}
@@ -75,7 +75,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
emit:
memcpy(item->header, newheader, sz);
- intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS);
+ intel_batchbuffer_data(brw->intel.batch, data, sz);
return GL_TRUE;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 06:39:04 +0000