diff options
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index d72b37b5854..ad9b421fff4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -3611,10 +3611,32 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr unsigned read_size = instr->const_index[1] - (instr->num_components - 1) * type_sz(dest.type); + fs_reg indirect_chv_high_32bit; + bool is_chv_bxt_64bit = + (devinfo->is_cherryview || devinfo->is_broxton) && + type_sz(dest.type) == 8; + if (is_chv_bxt_64bit) { + indirect_chv_high_32bit = vgrf(glsl_type::uint_type); + /* Calculate indirect address to read high 32 bits */ + bld.ADD(indirect_chv_high_32bit, indirect, brw_imm_ud(4)); + } + for (unsigned j = 0; j < instr->num_components; j++) { - bld.emit(SHADER_OPCODE_MOV_INDIRECT, - offset(dest, bld, j), offset(src, bld, j), - indirect, brw_imm_ud(read_size)); + if (!is_chv_bxt_64bit) { + bld.emit(SHADER_OPCODE_MOV_INDIRECT, + offset(dest, bld, j), offset(src, bld, j), + indirect, brw_imm_ud(read_size)); + } else { + bld.emit(SHADER_OPCODE_MOV_INDIRECT, + subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 0), + offset(src, bld, j), + indirect, brw_imm_ud(read_size)); + + bld.emit(SHADER_OPCODE_MOV_INDIRECT, + subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 1), + offset(src, bld, j), + indirect_chv_high_32bit, brw_imm_ud(read_size)); + } } } break; |