diff options
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu.h | 88 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_emit.c | 67 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_emit.c | 81 |
6 files changed, 139 insertions, 108 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 1d6ac2cea68..a415e378fff 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -32,6 +32,7 @@ #include "main/imports.h" #include "main/api_noop.h" +#include "main/macros.h" #include "main/vtxfmt.h" #include "main/simple_list.h" #include "shader/shader_api.h" @@ -128,9 +129,10 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; - ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT; - ctx->Const.MaxTextureCoordUnits = BRW_MAX_TEX_UNIT; + ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */ + ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits, + ctx->Const.MaxTextureImageUnits); ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */ /* Advertise the full hardware capabilities. The new memory diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 77980109cdf..5d3f99e025e 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -238,7 +238,7 @@ struct brw_vs_ouput_sizes { }; -#define BRW_MAX_TEX_UNIT 8 +#define BRW_MAX_TEX_UNIT 16 #define BRW_WM_MAX_SURF BRW_MAX_TEX_UNIT + MAX_DRAW_BUFFERS enum brw_cache_id { diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 49b422ee2ff..31e9ceb42ed 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -129,17 +129,28 @@ static INLINE int type_sz( GLuint type ) } } +/** + * Construct a brw_reg. + * \param file one of the BRW_x_REGISTER_FILE values + * \param nr register number/index + * \param subnr register sub number + * \param type one of BRW_REGISTER_TYPE_x + * \param vstride one of BRW_VERTICAL_STRIDE_x + * \param width one of BRW_WIDTH_x + * \param hstride one of BRW_HORIZONTAL_STRIDE_x + * \param swizzle one of BRW_SWIZZLE_x + * \param writemask WRITEMASK_X/Y/Z/W bitfield + */ static INLINE struct brw_reg brw_reg( GLuint file, - GLuint nr, - GLuint subnr, - GLuint type, - GLuint vstride, - GLuint width, - GLuint hstride, - GLuint swizzle, - GLuint writemask) -{ - + GLuint nr, + GLuint subnr, + GLuint type, + GLuint vstride, + GLuint width, + GLuint hstride, + GLuint swizzle, + GLuint writemask ) +{ struct brw_reg reg; reg.type = type; reg.file = file; @@ -166,6 +177,7 @@ static INLINE struct brw_reg brw_reg( GLuint file, return reg; } +/** Construct float[16] register */ static INLINE struct brw_reg brw_vec16_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -181,6 +193,7 @@ static INLINE struct brw_reg brw_vec16_reg( GLuint file, WRITEMASK_XYZW); } +/** Construct float[8] register */ static INLINE struct brw_reg brw_vec8_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -196,7 +209,7 @@ static INLINE struct brw_reg brw_vec8_reg( GLuint file, WRITEMASK_XYZW); } - +/** Construct float[4] register */ static INLINE struct brw_reg brw_vec4_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -212,7 +225,7 @@ static INLINE struct brw_reg brw_vec4_reg( GLuint file, WRITEMASK_XYZW); } - +/** Construct float[2] register */ static INLINE struct brw_reg brw_vec2_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -228,6 +241,7 @@ static INLINE struct brw_reg brw_vec2_reg( GLuint file, WRITEMASK_XY); } +/** Construct float[1] register */ static INLINE struct brw_reg brw_vec1_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -277,6 +291,7 @@ static INLINE struct brw_reg byte_offset( struct brw_reg reg, } +/** Construct unsigned word[16] register */ static INLINE struct brw_reg brw_uw16_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -284,6 +299,7 @@ static INLINE struct brw_reg brw_uw16_reg( GLuint file, return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); } +/** Construct unsigned word[8] register */ static INLINE struct brw_reg brw_uw8_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -291,6 +307,7 @@ static INLINE struct brw_reg brw_uw8_reg( GLuint file, return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); } +/** Construct unsigned word[1] register */ static INLINE struct brw_reg brw_uw1_reg( GLuint file, GLuint nr, GLuint subnr ) @@ -311,6 +328,7 @@ static INLINE struct brw_reg brw_imm_reg( GLuint type ) 0); } +/** Construct float immediate register */ static INLINE struct brw_reg brw_imm_f( GLfloat f ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); @@ -318,6 +336,7 @@ static INLINE struct brw_reg brw_imm_f( GLfloat f ) return imm; } +/** Construct integer immediate register */ static INLINE struct brw_reg brw_imm_d( GLint d ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); @@ -325,6 +344,7 @@ static INLINE struct brw_reg brw_imm_d( GLint d ) return imm; } +/** Construct uint immediate register */ static INLINE struct brw_reg brw_imm_ud( GLuint ud ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); @@ -332,6 +352,7 @@ static INLINE struct brw_reg brw_imm_ud( GLuint ud ) return imm; } +/** Construct ushort immediate register */ static INLINE struct brw_reg brw_imm_uw( GLushort uw ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); @@ -339,6 +360,7 @@ static INLINE struct brw_reg brw_imm_uw( GLushort uw ) return imm; } +/** Construct short immediate register */ static INLINE struct brw_reg brw_imm_w( GLshort w ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); @@ -350,8 +372,7 @@ static INLINE struct brw_reg brw_imm_w( GLshort w ) * numbers alias with _V and _VF below: */ -/* Vector of eight signed half-byte values: - */ +/** Construct vector of eight signed half-byte values */ static INLINE struct brw_reg brw_imm_v( GLuint v ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); @@ -362,8 +383,7 @@ static INLINE struct brw_reg brw_imm_v( GLuint v ) return imm; } -/* Vector of four 8-bit float values: - */ +/** Construct vector of four 8-bit float values */ static INLINE struct brw_reg brw_imm_vf( GLuint v ) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); @@ -400,44 +420,43 @@ static INLINE struct brw_reg brw_address( struct brw_reg reg ) return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr); } - -static INLINE struct brw_reg brw_vec1_grf( GLuint nr, - GLuint subnr ) +/** Construct float[1] general-purpose register */ +static INLINE struct brw_reg brw_vec1_grf( GLuint nr, GLuint subnr ) { return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } -static INLINE struct brw_reg brw_vec8_grf( GLuint nr, - GLuint subnr ) +/** Construct float[2] general-purpose register */ +static INLINE struct brw_reg brw_vec2_grf( GLuint nr, GLuint subnr ) { - return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } -static INLINE struct brw_reg brw_vec4_grf( GLuint nr, - GLuint subnr ) +/** Construct float[4] general-purpose register */ +static INLINE struct brw_reg brw_vec4_grf( GLuint nr, GLuint subnr ) { return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } - -static INLINE struct brw_reg brw_vec2_grf( GLuint nr, - GLuint subnr ) +/** Construct float[8] general-purpose register */ +static INLINE struct brw_reg brw_vec8_grf( GLuint nr, GLuint subnr ) { - return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } -static INLINE struct brw_reg brw_uw8_grf( GLuint nr, - GLuint subnr ) + +static INLINE struct brw_reg brw_uw8_grf( GLuint nr, GLuint subnr ) { return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } -static INLINE struct brw_reg brw_uw16_grf( GLuint nr, - GLuint subnr ) +static INLINE struct brw_reg brw_uw16_grf( GLuint nr, GLuint subnr ) { return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); } + +/** Construct null register (usually used for setting condition codes) */ static INLINE struct brw_reg brw_null_reg( void ) { return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, @@ -524,13 +543,13 @@ static INLINE struct brw_reg stride( struct brw_reg reg, GLuint width, GLuint hstride ) { - reg.vstride = cvt(vstride); reg.width = cvt(width) - 1; reg.hstride = cvt(hstride); return reg; } + static INLINE struct brw_reg vec16( struct brw_reg reg ) { return stride(reg, 16,16,1); @@ -556,6 +575,7 @@ static INLINE struct brw_reg vec1( struct brw_reg reg ) return stride(reg, 0,1,0); } + static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt ) { return vec1(suboffset(reg, elt)); @@ -687,7 +707,7 @@ static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset static INLINE struct brw_instruction *current_insn( struct brw_compile *p) { - return &p->store[p->nr_insn]; + return &p->store[p->nr_insn]; } void brw_pop_insn_state( struct brw_compile *p ); diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 4a9541378f7..80ff7437ba2 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -73,8 +73,6 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) c->prog_data.curb_read_length = reg - 1; - - /* Allocate input regs: */ c->nr_inputs = 0; @@ -84,8 +82,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0); reg++; } - } - + } /* Allocate outputs: TODO: could organize the non-position outputs * to go straight into message regs. @@ -339,6 +336,7 @@ static void emit_math1( struct brw_vs_compile *c, } } + static void emit_math2( struct brw_vs_compile *c, GLuint function, struct brw_reg dst, @@ -370,7 +368,6 @@ static void emit_math2( struct brw_vs_compile *c, release_tmp(c, tmp); } } - static void emit_exp_noalias( struct brw_vs_compile *c, @@ -521,8 +518,6 @@ static void emit_log_noalias( struct brw_vs_compile *c, } - - /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1 */ static void emit_dst_noalias( struct brw_vs_compile *c, @@ -544,6 +539,7 @@ static void emit_dst_noalias( struct brw_vs_compile *c, brw_MOV(p, brw_writemask(dst, WRITEMASK_W), arg1); } + static void emit_xpd( struct brw_compile *p, struct brw_reg dst, struct brw_reg t, @@ -554,7 +550,6 @@ static void emit_xpd( struct brw_compile *p, } - static void emit_lit_noalias( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0 ) @@ -596,7 +591,29 @@ static void emit_lit_noalias( struct brw_vs_compile *c, } +/** 3 or 4-component vector normalization */ +static void emit_nrm( struct brw_vs_compile *c, + struct brw_reg dst, + struct brw_reg arg0, + int num_comps) +{ + struct brw_compile *p = &c->func; + struct brw_reg tmp = get_tmp(c); + /* tmp = dot(arg0, arg0) */ + if (num_comps == 3) + brw_DP3(p, tmp, arg0, arg0); + else + brw_DP4(p, tmp, arg0, arg0); + + /* tmp = 1 / sqrt(tmp) */ + emit_math1(c, BRW_MATH_FUNCTION_RSQ, tmp, tmp, BRW_MATH_PRECISION_FULL); + + /* dst = arg0 * tmp */ + brw_MUL(p, dst, arg0, tmp); + + release_tmp(c, tmp); +} /* TODO: relative addressing! @@ -634,7 +651,6 @@ static struct brw_reg get_reg( struct brw_vs_compile *c, } - static struct brw_reg deref( struct brw_vs_compile *c, struct brw_reg arg, GLint offset) @@ -728,8 +744,6 @@ static struct brw_reg get_dst( struct brw_vs_compile *c, } - - static void emit_swz( struct brw_vs_compile *c, struct brw_reg dst, struct prog_src_register src ) @@ -801,8 +815,8 @@ static void emit_swz( struct brw_vs_compile *c, } - -/* Post-vertex-program processing. Send the results to the URB. +/** + * Post-vertex-program processing. Send the results to the URB. */ static void emit_vertex_write( struct brw_vs_compile *c) { @@ -817,7 +831,6 @@ static void emit_vertex_write( struct brw_vs_compile *c) get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG)); } - /* Build ndc coords */ if (!c->key.know_w_is_one) { ndc = get_tmp(c); @@ -848,7 +861,6 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8)); } - for (i = 0; i < c->key.nr_userclip; i++) { brw_set_conditionalmod(p, BRW_CONDITIONAL_L); brw_DP4(p, brw_null_reg(), pos, c->userplane[i]); @@ -856,7 +868,6 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_set_predicate_control(p, BRW_PREDICATE_NONE); } - /* i965 clipping workaround: * 1) Test for -ve rhw * 2) If set, @@ -888,14 +899,12 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), brw_imm_ud(0)); } - /* Emit the (interleaved) headers for the two vertices - an 8-reg * of zeros followed by two sets of NDC coordinates: */ brw_set_access_mode(p, BRW_ALIGN_1); brw_MOV(p, offset(m0, 2), ndc); brw_MOV(p, offset(m0, 3), pos); - brw_urb_WRITE(p, brw_null_reg(), /* dest */ @@ -909,9 +918,9 @@ static void emit_vertex_write( struct brw_vs_compile *c) 1, /* writes complete */ 0, /* urb destination offset */ BRW_URB_SWIZZLE_INTERLEAVE); - } + static void post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) { @@ -1035,6 +1044,12 @@ void brw_vs_emit(struct brw_vs_compile *c ) case OPCODE_DPH: brw_DPH(p, dst, args[0], args[1]); break; + case OPCODE_NRM3: + emit_nrm(c, dst, args[0], 3); + break; + case OPCODE_NRM4: + emit_nrm(c, dst, args[0], 4); + break; case OPCODE_DST: unalias2(c, dst, args[0], args[1], emit_dst_noalias); break; @@ -1102,7 +1117,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) break; case OPCODE_SGT: emit_sgt(p, dst, args[0], args[1]); - break; + break; case OPCODE_SLT: emit_slt(p, dst, args[0], args[1]); break; @@ -1136,7 +1151,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); brw_set_predicate_control_flag_value(p, 0xff); - break; + break; case OPCODE_CAL: brw_set_access_mode(p, BRW_ALIGN_1); brw_ADD(p, deref_1d(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); @@ -1145,7 +1160,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) get_addr_reg(stack_index), brw_imm_d(4)); inst->Data = &p->store[p->nr_insn]; brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); - break; + break; case OPCODE_RET: brw_ADD(p, get_addr_reg(stack_index), get_addr_reg(stack_index), brw_imm_d(-4)); @@ -1154,17 +1169,17 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_access_mode(p, BRW_ALIGN_16); case OPCODE_END: brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); - break; + break; case OPCODE_PRINT: case OPCODE_BGNSUB: case OPCODE_ENDSUB: + /* no-op instructions */ break; default: - _mesa_printf("Unsupported opcode %i (%s) in vertex shader\n", - inst->Opcode, inst->Opcode < MAX_OPCODE ? + _mesa_problem(NULL, "Unsupported opcode %i (%s) in vertex shader", + inst->Opcode, inst->Opcode < MAX_OPCODE ? _mesa_opcode_string(inst->Opcode) : "unknown"); - break; } if ((inst->DstReg.File == PROGRAM_OUTPUT) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index bad76793af7..5b4ee20ecb5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -36,6 +36,7 @@ #include "brw_state.h" +/** Return number of src args for given instruction */ GLuint brw_wm_nr_args( GLuint opcode ) { switch (opcode) { @@ -58,6 +59,8 @@ GLuint brw_wm_nr_args( GLuint opcode ) case OPCODE_TXP: case OPCODE_KIL: case OPCODE_LIT: + case OPCODE_NRM3: + case OPCODE_NRM4: case WM_CINTERP: case WM_WPOSXY: return 1; diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 58c78c4b2c5..b5050a3e40b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -194,7 +194,7 @@ static void emit_linterp( struct brw_compile *p, interp[2] = brw_vec1_grf(nr+1, 0); interp[3] = brw_vec1_grf(nr+1, 4); - for(i = 0; i < 4; i++ ) { + for (i = 0; i < 4; i++) { if (mask & (1<<i)) { brw_LINE(p, brw_null_reg(), interp[i], deltas[0]); brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]); @@ -219,42 +219,40 @@ static void emit_pinterp( struct brw_compile *p, interp[2] = brw_vec1_grf(nr+1, 0); interp[3] = brw_vec1_grf(nr+1, 4); - for(i = 0; i < 4; i++ ) { + for (i = 0; i < 4; i++) { if (mask & (1<<i)) { brw_LINE(p, brw_null_reg(), interp[i], deltas[0]); brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]); } } - for(i = 0; i < 4; i++ ) { + for (i = 0; i < 4; i++) { if (mask & (1<<i)) { brw_MUL(p, dst[i], dst[i], w[3]); } } } + static void emit_cinterp( struct brw_compile *p, const struct brw_reg *dst, GLuint mask, const struct brw_reg *arg0 ) { - struct brw_reg interp[4]; - GLuint nr = arg0[0].nr; - GLuint i; - - interp[0] = brw_vec1_grf(nr, 0); - interp[1] = brw_vec1_grf(nr, 4); - interp[2] = brw_vec1_grf(nr+1, 0); - interp[3] = brw_vec1_grf(nr+1, 4); - - for(i = 0; i < 4; i++ ) { - if (mask & (1<<i)) { - brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */ - } - } -} - + struct brw_reg interp[4]; + GLuint nr = arg0[0].nr; + GLuint i; + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + for (i = 0; i < 4; i++) { + if (mask & (1<<i)) { + brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */ + } + } +} static void emit_alu1( struct brw_compile *p, @@ -280,6 +278,7 @@ static void emit_alu1( struct brw_compile *p, brw_set_saturate(p, 0); } + static void emit_alu2( struct brw_compile *p, struct brw_instruction *(*func)(struct brw_compile *, struct brw_reg, @@ -351,6 +350,7 @@ static void emit_lrp( struct brw_compile *p, } } } + static void emit_sop( struct brw_compile *p, const struct brw_reg *dst, GLuint mask, @@ -376,7 +376,7 @@ static void emit_slt( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1); } static void emit_sle( struct brw_compile *p, @@ -385,7 +385,7 @@ static void emit_sle( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1); } static void emit_sgt( struct brw_compile *p, @@ -394,7 +394,7 @@ static void emit_sgt( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1); } static void emit_sge( struct brw_compile *p, @@ -403,7 +403,7 @@ static void emit_sge( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1); } static void emit_seq( struct brw_compile *p, @@ -412,7 +412,7 @@ static void emit_seq( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1); } static void emit_sne( struct brw_compile *p, @@ -421,7 +421,7 @@ static void emit_sne( struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { - emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1); + emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1); } static void emit_cmp( struct brw_compile *p, @@ -505,7 +505,7 @@ static void emit_dp3( struct brw_compile *p, const struct brw_reg *arg1 ) { if (!(mask & WRITEMASK_XYZW)) - return; /* Do not emit dead code*/ + return; /* Do not emit dead code */ assert((mask & WRITEMASK_XYZW) == WRITEMASK_X); @@ -525,7 +525,7 @@ static void emit_dp4( struct brw_compile *p, const struct brw_reg *arg1 ) { if (!(mask & WRITEMASK_XYZW)) - return; /* Do not emit dead code*/ + return; /* Do not emit dead code */ assert((mask & WRITEMASK_XYZW) == WRITEMASK_X); @@ -546,7 +546,7 @@ static void emit_dph( struct brw_compile *p, const struct brw_reg *arg1 ) { if (!(mask & WRITEMASK_XYZW)) - return; /* Do not emit dead code*/ + return; /* Do not emit dead code */ assert((mask & WRITEMASK_XYZW) == WRITEMASK_X); @@ -592,7 +592,7 @@ static void emit_math1( struct brw_compile *p, const struct brw_reg *arg0 ) { if (!(mask & WRITEMASK_XYZW)) - return; /* Do not emit dead code*/ + return; /* Do not emit dead code */ //assert((mask & WRITEMASK_XYZW) == WRITEMASK_X || // function == BRW_MATH_FUNCTION_SINCOS); @@ -619,7 +619,7 @@ static void emit_math2( struct brw_compile *p, const struct brw_reg *arg1) { if (!(mask & WRITEMASK_XYZW)) - return; /* Do not emit dead code*/ + return; /* Do not emit dead code */ assert((mask & WRITEMASK_XYZW) == WRITEMASK_X); @@ -760,7 +760,6 @@ static void emit_txb( struct brw_wm_compile *c, brw_MOV(p, brw_message_reg(8), arg[3]); msgLength = 9; - brw_SAMPLE(p, retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), 1, @@ -772,7 +771,6 @@ static void emit_txb( struct brw_wm_compile *c, 8, /* responseLength */ msgLength, 0); - } @@ -823,7 +821,6 @@ static void emit_kil( struct brw_wm_compile *c, struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); GLuint i; - /* XXX - usually won't need 4 compares! */ for (i = 0; i < 4; i++) { @@ -836,6 +833,7 @@ static void emit_kil( struct brw_wm_compile *c, } } + static void fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, @@ -869,6 +867,7 @@ static void fire_fb_write( struct brw_wm_compile *c, eot); } + static void emit_aa( struct brw_wm_compile *c, struct brw_reg *arg1, GLuint reg ) @@ -962,7 +961,6 @@ static void emit_fb_write( struct brw_wm_compile *c, nr += 2; } - if (!c->key.runtime_check_aads_emit) { if (c->key.aa_dest_stencil_reg) emit_aa(c, arg1, 2); @@ -996,8 +994,6 @@ static void emit_fb_write( struct brw_wm_compile *c, } - - /* Post-fragment-program processing. Send the results to the * framebuffer. */ @@ -1022,6 +1018,7 @@ static void emit_spill( struct brw_wm_compile *c, slot); } + static void emit_unspill( struct brw_wm_compile *c, struct brw_reg reg, GLuint slot ) @@ -1047,7 +1044,6 @@ static void emit_unspill( struct brw_wm_compile *c, } - /** * Retrieve upto 4 GEN4 register pairs for the given wm reg: */ @@ -1073,6 +1069,7 @@ static void get_argument_regs( struct brw_wm_compile *c, } } + static void spill_values( struct brw_wm_compile *c, struct brw_wm_value *values, GLuint nr ) @@ -1085,7 +1082,6 @@ static void spill_values( struct brw_wm_compile *c, } - /* Emit the fragment program instructions here. */ void brw_wm_emit( struct brw_wm_compile *c ) @@ -1176,7 +1172,7 @@ void brw_wm_emit( struct brw_wm_compile *c ) emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]); break; - case OPCODE_DP3: /* */ + case OPCODE_DP3: emit_dp3(p, dst, dst_flags, args[0], args[1]); break; @@ -1188,7 +1184,7 @@ void brw_wm_emit( struct brw_wm_compile *c ) emit_dph(p, dst, dst_flags, args[0], args[1]); break; - case OPCODE_LRP: /* */ + case OPCODE_LRP: emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]); break; @@ -1315,8 +1311,3 @@ void brw_wm_emit( struct brw_wm_compile *c ) inst->dst[i]->spill_slot); } } - - - - - |