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-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.cpp10
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_blit.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_surface_formats.c72
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c6
-rw-r--r--src/mesa/drivers/dri/i965/intel_fbo.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c22
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h2
-rw-r--r--src/mesa/drivers/dri/i965/intel_screen.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_subimage.c4
12 files changed, 72 insertions, 72 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index e7f6328d431..e1b782dbba2 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -87,7 +87,7 @@ brw_blorp_surface_info::set(struct brw_context *brw,
this->msaa_layout = mt->msaa_layout;
switch (mt->format) {
- case MESA_FORMAT_S8:
+ case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
* program swizzle the coordinates.
@@ -108,10 +108,10 @@ brw_blorp_surface_info::set(struct brw_context *brw,
*/
this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
break;
- case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z_FLOAT32:
this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
break;
- case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z_UNORM16:
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
@@ -326,8 +326,8 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
assert(intel_miptree_slice_has_hiz(mt, level, layer));
switch (mt->format) {
- case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
- case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
+ case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
+ case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
case MESA_FORMAT_X8_Z24: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
default: assert(0); break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 1030e4e0afd..db41497732e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -134,11 +134,11 @@ public:
/* Setting this flag indicates that the buffer's contents are W-tiled
* stencil data, but the surface state should be set up for Y tiled
- * MESA_FORMAT_R8 data (this is necessary because surface states don't
+ * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
* support W tiling).
*
* Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
- * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
+ * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
* pitch stored in the surface state will be multiplied by 2, and the
* height will be halved. Also, since W and Y tiles store their data in a
* different order, the width and height will be rounded up to a multiple
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index d8df4afd08f..55ff1e6bfb2 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2030,7 +2030,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
break;
case GL_UNSIGNED_INT:
- if (src_mt->format == MESA_FORMAT_S8) {
+ if (src_mt->format == MESA_FORMAT_S_UINT8) {
/* We process stencil as though it's an unsigned normalized color */
wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 659d339e1a5..b463be86ac6 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -141,11 +141,11 @@ brw_fast_clear_depth(struct gl_context *ctx)
*/
return false;
- case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z_FLOAT32:
depth_clear_value = float_as_int(ctx->Depth.Clear);
break;
- case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z_UNORM16:
/* From the Sandy Bridge PRM, volume 2 part 1, page 314:
*
* "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 2375993beaf..438637447de 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -151,9 +151,9 @@ brw_depthbuffer_format(struct brw_context *brw)
return BRW_DEPTHFORMAT_D32_FLOAT;
switch (drb->mt->format) {
- case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z_UNORM16:
return BRW_DEPTHFORMAT_D16_UNORM;
- case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z_FLOAT32:
return BRW_DEPTHFORMAT_D32_FLOAT;
case MESA_FORMAT_X8_Z24:
if (brw->gen >= 6) {
@@ -230,7 +230,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
if (stencil_mt->stencil_mt)
stencil_mt = stencil_mt->stencil_mt;
- if (stencil_mt->format == MESA_FORMAT_S8) {
+ if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
/* Separate stencil buffer uses 64x64 tiles. */
tile_mask_x |= 63;
tile_mask_y |= 63;
@@ -494,7 +494,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
stencil_mt = get_stencil_miptree(stencil_irb);
brw->depthstencil.stencil_mt = stencil_mt;
- if (stencil_mt->format == MESA_FORMAT_S8) {
+ if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
/* Note: we can't compute the stencil offset using
* intel_region_get_aligned_offset(), because stencil_region claims
* that the region is untiled even though it's W tiled.
@@ -526,7 +526,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
uint32_t width = 1, height = 1;
if (stencil_mt) {
- separate_stencil = stencil_mt->format == MESA_FORMAT_S8;
+ separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8;
/* Gen7 supports only separate stencil */
assert(separate_stencil || brw->gen < 7);
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 566d68834f7..651c0f96217 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -327,8 +327,8 @@ brw_format_for_mesa_format(mesa_format mesa_format)
[MESA_FORMAT_R8G8B8X8_UNORM] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
[MESA_FORMAT_B8G8R8X8_UNORM] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
[MESA_FORMAT_X8R8G8B8_UNORM] = 0,
- [MESA_FORMAT_RGB888] = 0,
- [MESA_FORMAT_BGR888] = BRW_SURFACEFORMAT_R8G8B8_UNORM,
+ [MESA_FORMAT_BGR_UNORM8] = 0,
+ [MESA_FORMAT_RGB_UNORM8] = BRW_SURFACEFORMAT_R8G8B8_UNORM,
[MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
[MESA_FORMAT_RGB565_REV] = 0,
[MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
@@ -342,33 +342,33 @@ brw_format_for_mesa_format(mesa_format mesa_format)
[MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
[MESA_FORMAT_AL1616_REV] = 0,
[MESA_FORMAT_RGB332] = 0,
- [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
- [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
- [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
- [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
- [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
- [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
+ [MESA_FORMAT_A_UNORM8] = BRW_SURFACEFORMAT_A8_UNORM,
+ [MESA_FORMAT_A_UNORM16] = BRW_SURFACEFORMAT_A16_UNORM,
+ [MESA_FORMAT_L_UNORM8] = BRW_SURFACEFORMAT_L8_UNORM,
+ [MESA_FORMAT_L_UNORM16] = BRW_SURFACEFORMAT_L16_UNORM,
+ [MESA_FORMAT_I_UNORM8] = BRW_SURFACEFORMAT_I8_UNORM,
+ [MESA_FORMAT_I_UNORM16] = BRW_SURFACEFORMAT_I16_UNORM,
[MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
[MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
- [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
+ [MESA_FORMAT_R_UNORM8] = BRW_SURFACEFORMAT_R8_UNORM,
[MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
[MESA_FORMAT_RG88] = 0,
- [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
+ [MESA_FORMAT_R_UNORM16] = BRW_SURFACEFORMAT_R16_UNORM,
[MESA_FORMAT_GR1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
[MESA_FORMAT_RG1616] = 0,
[MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
[MESA_FORMAT_Z24_S8] = 0,
[MESA_FORMAT_S8_Z24] = 0,
- [MESA_FORMAT_Z16] = 0,
+ [MESA_FORMAT_Z_UNORM16] = 0,
[MESA_FORMAT_X8_Z24] = 0,
[MESA_FORMAT_Z24_X8] = 0,
- [MESA_FORMAT_Z32] = 0,
- [MESA_FORMAT_S8] = 0,
+ [MESA_FORMAT_Z_UNORM32] = 0,
+ [MESA_FORMAT_S_UINT8] = 0,
- [MESA_FORMAT_SRGB8] = 0,
+ [MESA_FORMAT_BGR_SRGB8] = 0,
[MESA_FORMAT_SRGBA8] = 0,
[MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
- [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
+ [MESA_FORMAT_L_SRGB8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
[MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
[MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
[MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
@@ -463,7 +463,7 @@ brw_format_for_mesa_format(mesa_format mesa_format)
[MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
[MESA_FORMAT_SIGNED_RGB_16] = BRW_SURFACEFORMAT_R16G16B16_SNORM,
[MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
- [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
+ [MESA_FORMAT_RGBA_UNORM16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
[MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
[MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
@@ -499,7 +499,7 @@ brw_format_for_mesa_format(mesa_format mesa_format)
[MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
[MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
- [MESA_FORMAT_Z32_FLOAT] = 0,
+ [MESA_FORMAT_Z_FLOAT32] = 0,
[MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
[MESA_FORMAT_ARGB2101010_UINT] = BRW_SURFACEFORMAT_B10G10R10A2_UINT,
@@ -509,17 +509,17 @@ brw_format_for_mesa_format(mesa_format mesa_format)
[MESA_FORMAT_XRGB1555_UNORM] = BRW_SURFACEFORMAT_B5G5R5X1_UNORM,
[MESA_FORMAT_XBGR8888_SNORM] = 0,
[MESA_FORMAT_XBGR8888_SRGB] = 0,
- [MESA_FORMAT_XBGR8888_UINT] = 0,
- [MESA_FORMAT_XBGR8888_SINT] = 0,
+ [MESA_FORMAT_RGBX_UINT8] = 0,
+ [MESA_FORMAT_RGBX_SINT8] = 0,
[MESA_FORMAT_XRGB2101010_UNORM] = BRW_SURFACEFORMAT_B10G10R10X2_UNORM,
- [MESA_FORMAT_XBGR16161616_UNORM] = BRW_SURFACEFORMAT_R16G16B16X16_UNORM,
- [MESA_FORMAT_XBGR16161616_SNORM] = 0,
- [MESA_FORMAT_XBGR16161616_FLOAT] = BRW_SURFACEFORMAT_R16G16B16X16_FLOAT,
- [MESA_FORMAT_XBGR16161616_UINT] = 0,
- [MESA_FORMAT_XBGR16161616_SINT] = 0,
- [MESA_FORMAT_XBGR32323232_FLOAT] = BRW_SURFACEFORMAT_R32G32B32X32_FLOAT,
- [MESA_FORMAT_XBGR32323232_UINT] = 0,
- [MESA_FORMAT_XBGR32323232_SINT] = 0,
+ [MESA_FORMAT_RGBX_UNORM16] = BRW_SURFACEFORMAT_R16G16B16X16_UNORM,
+ [MESA_FORMAT_RGBX_SNORM16] = 0,
+ [MESA_FORMAT_RGBX_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16X16_FLOAT,
+ [MESA_FORMAT_RGBX_UINT16] = 0,
+ [MESA_FORMAT_RGBX_SINT16] = 0,
+ [MESA_FORMAT_RGBX_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32X32_FLOAT,
+ [MESA_FORMAT_RGBX_UINT32] = 0,
+ [MESA_FORMAT_RGBX_SINT32] = 0,
};
assert(mesa_format < MESA_FORMAT_COUNT);
return table[mesa_format];
@@ -602,9 +602,9 @@ brw_init_surface_formats(struct brw_context *brw)
*/
brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
+ brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true;
+ brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true;
+ brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true;
brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
/* We remap depth formats to a supported texturing format in
@@ -612,7 +612,7 @@ brw_init_surface_formats(struct brw_context *brw)
*/
ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
- ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
+ ctx->TextureFormatSupported[MESA_FORMAT_Z_FLOAT32] = true;
ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
/* It appears that Z16 is slower than Z24 (on Intel Ivybridge and newer
@@ -627,7 +627,7 @@ brw_init_surface_formats(struct brw_context *brw)
* asking for DEPTH_COMPONENT16, so we have to respect that.
*/
if (_mesa_is_desktop_gl(ctx))
- ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
+ ctx->TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
/* On hardware that lacks support for ETC1, we map ETC1 to RGBX
* during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
@@ -694,14 +694,14 @@ translate_tex_format(struct brw_context *brw,
switch( mesa_format ) {
- case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z_UNORM16:
return BRW_SURFACEFORMAT_R16_UNORM;
case MESA_FORMAT_S8_Z24:
case MESA_FORMAT_X8_Z24:
return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
- case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z_FLOAT32:
return BRW_SURFACEFORMAT_R32_FLOAT;
case MESA_FORMAT_Z32_FLOAT_X24S8:
@@ -738,11 +738,11 @@ brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format)
return false;
switch (format) {
- case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z_FLOAT32:
case MESA_FORMAT_Z32_FLOAT_X24S8:
case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z16:
+ case MESA_FORMAT_Z_UNORM16:
return true;
default:
return false;
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index a7e4ddd3a28..61a2eba2f54 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -75,10 +75,10 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
return i;
}
- if (format == MESA_FORMAT_S8)
+ if (format == MESA_FORMAT_S_UINT8)
return 8;
- if (brw->gen >= 7 && format == MESA_FORMAT_Z16)
+ if (brw->gen >= 7 && format == MESA_FORMAT_Z_UNORM16)
return 8;
return 4;
@@ -114,7 +114,7 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
if (_mesa_is_format_compressed(format))
return 4;
- if (format == MESA_FORMAT_S8)
+ if (format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 961bbc28386..5f6e1b3c391 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -206,7 +206,7 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
case GL_STENCIL_INDEX16_EXT:
/* These aren't actual texture formats, so force them here. */
if (brw->has_separate_stencil) {
- rb->Format = MESA_FORMAT_S8;
+ rb->Format = MESA_FORMAT_S_UINT8;
} else {
assert(!brw->must_use_separate_stencil);
rb->Format = MESA_FORMAT_S8_Z24;
@@ -609,7 +609,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
fbo_incomplete(fb, "FBO incomplete: separate stencil "
"unsupported\n");
}
- if (stencil_mt->format != MESA_FORMAT_S8) {
+ if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
fbo_incomplete(fb, "FBO incomplete: separate stencil is %s "
"instead of S8\n",
_mesa_get_format_name(stencil_mt->format));
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 9f3c9a76f07..2a84391f732 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -353,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
- MESA_FORMAT_S8,
+ MESA_FORMAT_S_UINT8,
mt->first_level,
mt->last_level,
mt->logical_width0,
@@ -373,7 +373,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (mt->format == MESA_FORMAT_S8_Z24) {
mt->format = MESA_FORMAT_X8_Z24;
} else if (mt->format == MESA_FORMAT_Z32_FLOAT_X24S8) {
- mt->format = MESA_FORMAT_Z32_FLOAT;
+ mt->format = MESA_FORMAT_Z_FLOAT32;
mt->cpp = 4;
} else {
_mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
@@ -397,7 +397,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
enum intel_miptree_tiling_mode requested,
struct intel_mipmap_tree *mt)
{
- if (format == MESA_FORMAT_S8) {
+ if (format == MESA_FORMAT_S_UINT8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
* non-tiled buffer because the GTT is incapable of W fencing.
*/
@@ -519,7 +519,7 @@ intel_miptree_create(struct brw_context *brw,
format = MESA_FORMAT_R8G8B8A8_UNORM;
break;
case MESA_FORMAT_ETC2_R11_EAC:
- format = MESA_FORMAT_R16;
+ format = MESA_FORMAT_R_UNORM16;
break;
case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
format = MESA_FORMAT_SIGNED_R16;
@@ -553,7 +553,7 @@ intel_miptree_create(struct brw_context *brw,
total_width = mt->total_width;
total_height = mt->total_height;
- if (format == MESA_FORMAT_S8) {
+ if (format == MESA_FORMAT_S_UINT8) {
/* Align to size of W tile, 64x64. */
total_width = ALIGN(total_width, 64);
total_height = ALIGN(total_height, 64);
@@ -920,7 +920,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
mesa_format mt_format = mt->format;
if (mt->format == MESA_FORMAT_X8_Z24 && mt->stencil_mt)
mt_format = MESA_FORMAT_S8_Z24;
- if (mt->format == MESA_FORMAT_Z32_FLOAT && mt->stencil_mt)
+ if (mt->format == MESA_FORMAT_Z_FLOAT32 && mt->stencil_mt)
mt_format = MESA_FORMAT_Z32_FLOAT_X24S8;
if (mt->etc_format != MESA_FORMAT_NONE)
mt_format = mt->etc_format;
@@ -1221,7 +1221,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
/* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
* each sample).
*/
- format = MESA_FORMAT_R8;
+ format = MESA_FORMAT_R_UNORM8;
break;
case 8:
/* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
@@ -2066,7 +2066,7 @@ intel_miptree_map_depthstencil(struct brw_context *brw,
{
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
- bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
+ bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
int packed_bpp = map_z32f_x24s8 ? 8 : 4;
map->stride = map->w * packed_bpp;
@@ -2138,7 +2138,7 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw,
{
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
- bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
+ bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
if (map->mode & GL_MAP_WRITE_BIT) {
uint32_t *packed_map = map->ptr;
@@ -2279,7 +2279,7 @@ intel_miptree_map_singlesample(struct brw_context *brw,
intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice);
}
- if (mt->format == MESA_FORMAT_S8) {
+ if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_map_s8(brw, mt, map, level, slice);
} else if (mt->etc_format != MESA_FORMAT_NONE &&
!(mode & BRW_MAP_DIRECT_BIT)) {
@@ -2330,7 +2330,7 @@ intel_miptree_unmap_singlesample(struct brw_context *brw,
DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__,
mt, _mesa_get_format_name(mt->format), level, slice);
- if (mt->format == MESA_FORMAT_S8) {
+ if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_unmap_s8(brw, mt, map, level, slice);
} else if (mt->etc_format != MESA_FORMAT_NONE &&
!(map->mode & BRW_MAP_DIRECT_BIT)) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 722e346c661..cb2eda60a54 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -279,7 +279,7 @@ struct intel_mipmap_tree
* on hardware where we want or need to use separate stencil, there will be
* two miptrees for storing the data. If the depthstencil texture or rb is
* MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
- * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
+ * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_S8_Z24 objects it will be
* MESA_FORMAT_X8_Z24.
*
* For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 2f2d478d156..1b884cbcad4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1007,7 +1007,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
rb = intel_create_private_renderbuffer(MESA_FORMAT_X8_Z24,
num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
- rb = intel_create_private_renderbuffer(MESA_FORMAT_S8,
+ rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8,
num_samples);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
} else {
@@ -1023,7 +1023,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
}
else if (mesaVis->depthBits == 16) {
assert(mesaVis->stencilBits == 0);
- rb = intel_create_private_renderbuffer(MESA_FORMAT_Z16,
+ rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16,
num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 1def8ca9f58..ce8bbe17e02 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -572,8 +572,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
packing->Invert)
return false;
- if ((texImage->TexFormat == MESA_FORMAT_L8 && format == GL_LUMINANCE) ||
- (texImage->TexFormat == MESA_FORMAT_A8 && format == GL_ALPHA)) {
+ if ((texImage->TexFormat == MESA_FORMAT_L_UNORM8 && format == GL_LUMINANCE) ||
+ (texImage->TexFormat == MESA_FORMAT_A_UNORM8 && format == GL_ALPHA)) {
cpp = 1;
mem_copy = memcpy;
} else if ((texImage->TexFormat == MESA_FORMAT_B8G8R8A8_UNORM) ||
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 06:18:17 +0000