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Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 07e798264a4..2ab0faa632c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -136,7 +136,7 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
{
switch (mt->tiling) {
default:
- assert(!"Non-MSRT MCS requires X or Y tiling");
+ unreachable("Non-MSRT MCS requires X or Y tiling");
/* In release builds, fall through */
case I915_TILING_Y:
*width_px = 32 / mt->cpp;
@@ -322,7 +322,7 @@ intel_miptree_create_layout(struct brw_context *brw,
/* num_samples should already have been quantized to 0, 1, 2, 4, or
* 8.
*/
- assert(false);
+ unreachable("not reached");
}
} else {
/* Non-interleaved */
@@ -987,7 +987,7 @@ intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
switch (tiling) {
default:
- assert(false);
+ unreachable("not reached");
case I915_TILING_NONE:
*mask_x = *mask_y = 0;
break;
@@ -1031,7 +1031,7 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
switch (tiling) {
default:
- assert(false);
+ unreachable("not reached");
case I915_TILING_NONE:
return y * pitch + x * cpp;
case I915_TILING_X:
@@ -1257,8 +1257,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
format = MESA_FORMAT_R_UINT32;
break;
default:
- assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
- return false;
+ unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
};
/* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":