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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_pipe_control.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_pipe_control.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 95fb86bd616..dbeb0acc20e 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -124,7 +124,8 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,
- brw->workaround_bo, 0, 0);
+ brw->workaround_bo,
+ brw->workaround_bo_offset, 0);
}
/**
@@ -192,7 +193,8 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0);
+ brw->workaround_bo,
+ brw->workaround_bo_offset, 0);
}
/**
@@ -240,7 +242,8 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0);
+ brw->workaround_bo,
+ brw->workaround_bo_offset, 0);
}
/*
@@ -298,7 +301,8 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
brw_emit_pipe_control_write(brw,
flags | PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0);
+ brw->workaround_bo,
+ brw->workaround_bo_offset, 0);
if (devinfo->is_haswell) {
/* Haswell needs addition work-arounds:
@@ -335,7 +339,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
* 3DPRIMITIVE when needed anyway.
*/
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
- brw->workaround_bo, 0);
+ brw->workaround_bo, brw->workaround_bo_offset);
}
} else {
/* On gen4-5, a regular pipe control seems to suffice. */
@@ -414,6 +418,7 @@ brw_init_pipe_control(struct brw_context *brw,
if (brw->workaround_bo == NULL)
return -ENOMEM;
+ brw->workaround_bo_offset = 0;
brw->pipe_controls_since_last_cs_stall = 0;
return 0;