1 files changed, 36 insertions, 36 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index cf1c385f098..5f83470ea92 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -313,7 +313,7 @@ fs_inst *
 fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
                enum brw_conditional_mod condition)
 {
-   assert(brw->gen == 6);
+   assert(devinfo->gen == 6);
    fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
                                         reg_null_d, src0, src1);
    inst->conditional_mod = condition;
@@ -405,7 +405,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
                               varying_offset, fs_reg(const_offset & ~3)));
 
    int scale = 1;
-   if (brw->gen == 4 && dst.width == 8) {
+   if (devinfo->gen == 4 && dst.width == 8) {
       /* Pre-gen5, we can either use a SIMD8 message that requires (header,
        * u, v, r) as parameters, or we can just use the SIMD16 message
        * consisting of (header, u).  We choose the second, at the cost of a
@@ -415,7 +415,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
    }
 
    enum opcode op;
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
       op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
    else
       op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
@@ -428,10 +428,10 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
    inst->regs_written = regs_written;
    instructions.push_tail(inst);
 
-   if (brw->gen < 7) {
+   if (devinfo->gen < 7) {
       inst->base_mrf = 13;
       inst->header_present = true;
-      if (brw->gen == 4)
+      if (devinfo->gen == 4)
          inst->mlen = 3;
       else
          inst->mlen = 1 + dispatch_width / 8;
@@ -517,9 +517,9 @@ fs_inst::is_send_from_grf() const
 }
 
 bool
-fs_inst::can_do_source_mods(struct brw_context *brw)
+fs_inst::can_do_source_mods(const struct brw_device_info *devinfo)
 {
-   if (brw->gen == 6 && is_math())
+   if (devinfo->gen == 6 && is_math())
       return false;
 
    if (is_send_from_grf())
@@ -689,7 +689,7 @@ fs_visitor::type_size(const struct glsl_type *type)
 fs_reg
 fs_visitor::get_timestamp(fs_inst **out_mov)
 {
-   assert(brw->gen >= 7);
+   assert(devinfo->gen >= 7);
 
    fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
                                           BRW_ARF_TIMESTAMP,
@@ -1261,7 +1261,7 @@ fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer,
    wpos = offset(wpos, 1);
 
    /* gl_FragCoord.z */
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       emit(MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0))));
    } else {
       emit(FS_OPCODE_LINTERP, wpos,
@@ -1282,7 +1282,7 @@ fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp,
                          bool is_centroid, bool is_sample)
 {
    brw_wm_barycentric_interp_mode barycoord_mode;
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       if (is_centroid) {
          if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
             barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
@@ -1372,7 +1372,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
 	    /* Smooth/noperspective interpolation case. */
 	    for (unsigned int k = 0; k < type->vector_elements; k++) {
                struct brw_reg interp = interp_reg(location, k);
-               if (brw->needs_unlit_centroid_workaround && mod_centroid) {
+               if (devinfo->needs_unlit_centroid_workaround && mod_centroid) {
                   /* Get the pixel/sample mask into f0 so that we know
                    * which pixels are lit.  Then, for each channel that is
                    * unlit, replace the centroid data with non-centroid
@@ -1385,7 +1385,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                       false, false);
                   inst->predicate = BRW_PREDICATE_NORMAL;
                   inst->predicate_inverse = true;
-                  if (brw->has_pln)
+                  if (devinfo->has_pln)
                      inst->no_dd_clear = true;
 
                   inst = emit_linterp(attr, fs_reg(interp), interpolation_mode,
@@ -1393,7 +1393,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                       mod_sample || key->persample_shading);
                   inst->predicate = BRW_PREDICATE_NORMAL;
                   inst->predicate_inverse = false;
-                  if (brw->has_pln)
+                  if (devinfo->has_pln)
                      inst->no_dd_check = true;
 
                } else {
@@ -1401,7 +1401,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                mod_centroid && !key->persample_shading,
                                mod_sample || key->persample_shading);
                }
-               if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
+               if (devinfo->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
                   emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
                }
 	       attr = offset(attr, 1);
@@ -1418,7 +1418,7 @@ fs_visitor::emit_frontfacing_interpolation()
 {
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::bool_type));
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
        * a boolean result from this (~0/true or 0/false).
        *
@@ -1480,7 +1480,7 @@ fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
 fs_reg *
 fs_visitor::emit_samplepos_setup()
 {
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    this->current_annotation = "compute sample position";
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::vec2_type));
@@ -1531,7 +1531,7 @@ fs_visitor::emit_sampleid_setup()
 {
    assert(stage == MESA_SHADER_FRAGMENT);
    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    this->current_annotation = "compute sample id";
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
@@ -1607,14 +1607,14 @@ fs_visitor::fix_math_operand(fs_reg src)
     * The hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (brw->gen == 6 && src.file != UNIFORM && src.file != IMM &&
+   if (devinfo->gen == 6 && src.file != UNIFORM && src.file != IMM &&
        !src.abs && !src.negate)
       return src;
 
    /* Gen7 relaxes most of the above restrictions, but still can't use IMM
     * operands to math
     */
-   if (brw->gen >= 7 && src.file != IMM)
+   if (devinfo->gen >= 7 && src.file != IMM)
       return src;
 
    fs_reg expanded = vgrf(glsl_type::float_type);
@@ -1647,12 +1647,12 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
     * Gen 6 hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (brw->gen == 6 || brw->gen == 7)
+   if (devinfo->gen == 6 || devinfo->gen == 7)
       src = fix_math_operand(src);
 
    fs_inst *inst = emit(opcode, dst, src);
 
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       inst->base_mrf = 2;
       inst->mlen = dispatch_width / 8;
    }
@@ -1666,9 +1666,9 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
    int base_mrf = 2;
    fs_inst *inst;
 
-   if (brw->gen >= 8) {
+   if (devinfo->gen >= 8) {
       inst = emit(opcode, dst, src0, src1);
-   } else if (brw->gen >= 6) {
+   } else if (devinfo->gen >= 6) {
       src0 = fix_math_operand(src0);
       src1 = fix_math_operand(src1);
 
@@ -1768,7 +1768,7 @@ fs_visitor::calculate_urb_setup()
 
    int urb_next = 0;
    /* Figure out where each of the incoming setup attributes lands. */
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       if (_mesa_bitcount_64(prog->InputsRead &
                             BRW_FS_VARYING_INPUT_MASK) <= 16) {
          /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
@@ -2548,7 +2548,7 @@ fs_visitor::opt_sampler_eot()
 {
    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 
-   if (brw->gen < 9 && !brw->is_cherryview)
+   if (devinfo->gen < 9 && !devinfo->is_cherryview)
       return false;
 
    /* FINISHME: It should be possible to implement this optimization when there
@@ -2732,7 +2732,7 @@ fs_visitor::compute_to_mrf()
    int next_ip = 0;
 
    /* No MRFs on Gen >= 7. */
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
       return false;
 
    calculate_live_intervals();
@@ -2797,7 +2797,7 @@ fs_visitor::compute_to_mrf()
 	    if (scan_inst->mlen)
 	       break;
 
-	    if (brw->gen == 6) {
+	    if (devinfo->gen == 6) {
 	       /* gen6 math instructions must have the destination be
 		* GRF, so no compute-to-MRF for them.
 		*/
@@ -3164,7 +3164,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins
 void
 fs_visitor::insert_gen4_send_dependency_workarounds()
 {
-   if (brw->gen != 4 || brw->is_g4x)
+   if (devinfo->gen != 4 || devinfo->is_g4x)
       return;
 
    bool progress = false;
@@ -3208,7 +3208,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
       if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
          continue;
 
-      if (brw->gen >= 7) {
+      if (devinfo->gen >= 7) {
          /* The offset arg before was a vec4-aligned byte offset.  We need to
           * turn it into a dword offset.
           */
@@ -3221,7 +3221,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
          /* We have to use a message header on Skylake to get SIMD4x2 mode.
           * Reserve space for the register.
           */
-         if (brw->gen >= 9) {
+         if (devinfo->gen >= 9) {
             payload.reg_offset++;
             alloc.sizes[payload.reg] = 2;
          }
@@ -3306,7 +3306,7 @@ fs_visitor::lower_load_payload()
                /* Do nothing but otherwise increment as normal */
             } else if (dst.file == MRF &&
                        dst.width == 8 &&
-                       brw->has_compr4 &&
+                       devinfo->has_compr4 &&
                        i + 4 < inst->sources &&
                        inst->src[i + 4].equals(horiz_offset(inst->src[i], 8))) {
                fs_reg compr4_dst = dst;
@@ -3427,7 +3427,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
    if (inst->conditional_mod) {
       fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
       if (!inst->predicate &&
-          (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+          (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
                               inst->opcode != BRW_OPCODE_IF &&
                               inst->opcode != BRW_OPCODE_WHILE))) {
          fprintf(file, ".f0.%d", inst->flag_subreg);
@@ -3646,7 +3646,7 @@ fs_visitor::setup_payload_gen6()
       (stage == MESA_SHADER_FRAGMENT) ?
       ((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
 
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    /* R0-1: masks, pixel X/Y coordinates. */
    payload.num_regs = 2;
@@ -3701,7 +3701,7 @@ fs_visitor::setup_payload_gen6()
 
    /* R32: MSAA input coverage mask */
    if (prog->SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
-      assert(brw->gen >= 7);
+      assert(devinfo->gen >= 7);
       payload.sample_mask_in_reg = payload.num_regs;
       payload.num_regs++;
       if (dispatch_width == 16) {
@@ -3978,7 +3978,7 @@ fs_visitor::run_fs()
 
    assign_binding_table_offsets();
 
-   if (brw->gen >= 6)
+   if (devinfo->gen >= 6)
       setup_payload_gen6();
    else
       setup_payload_gen4();
@@ -3993,7 +3993,7 @@ fs_visitor::run_fs()
 
       calculate_urb_setup();
       if (prog->InputsRead > 0) {
-         if (brw->gen < 6)
+         if (devinfo->gen < 6)
             emit_interpolation_setup_gen4();
          else
             emit_interpolation_setup_gen6();