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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 07f1d48ff65..9e0e2423dae 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -372,19 +372,22 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
front_irb->need_downsample = true;
if (back_irb)
back_irb->need_downsample = true;
- if (depth_irb && brw_depth_writes_enabled(brw)) {
+ if (depth_irb) {
+ bool depth_written = brw_depth_writes_enabled(brw);
if (depth_att->Layered) {
- for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
- intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
- depth_irb->mt_level,
- depth_irb->mt_layer + layer);
- }
+ intel_miptree_finish_depth(brw, depth_irb->mt,
+ depth_irb->mt_level,
+ depth_irb->mt_layer,
+ depth_irb->layer_count,
+ depth_written);
} else {
- intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
- depth_irb->mt_level,
- depth_irb->mt_layer);
+ intel_miptree_finish_depth(brw, depth_irb->mt,
+ depth_irb->mt_level,
+ depth_irb->mt_layer, 1,
+ depth_written);
}
- brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
+ if (depth_written)
+ brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
}
if (ctx->Extensions.ARB_stencil_texturing &&