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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_blorp.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.cpp32
1 files changed, 31 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 95f039f63db..762d7350632 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -35,6 +35,11 @@ brw_blorp_mip_info::brw_blorp_mip_info()
{
}
+brw_blorp_surface_info::brw_blorp_surface_info()
+ : map_stencil_as_y_tiled(false)
+{
+}
+
void
brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer)
@@ -47,6 +52,23 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
}
void
+brw_blorp_surface_info::set(struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer)
+{
+ brw_blorp_mip_info::set(mt, level, layer);
+
+ if (mt->format == MESA_FORMAT_S8) {
+ /* The miptree is a W-tiled stencil buffer. Surface states can't be set
+ * up for W tiling, so we'll need to use Y tiling and have the WM
+ * program swizzle the coordinates.
+ */
+ this->map_stencil_as_y_tiled = true;
+ } else {
+ this->map_stencil_as_y_tiled = false;
+ }
+}
+
+void
brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
{
/* Construct a dummy renderbuffer just to extract tile offsets. */
@@ -65,7 +87,8 @@ brw_blorp_params::brw_blorp_params()
x1(0),
y1(0),
depth_format(0),
- hiz_op(GEN6_HIZ_OP_NONE)
+ hiz_op(GEN6_HIZ_OP_NONE),
+ use_wm_prog(false)
{
}
@@ -106,3 +129,10 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
default: assert(0); break;
}
}
+
+uint32_t
+brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
+ brw_blorp_prog_data **prog_data) const
+{
+ return 0;
+}