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-rw-r--r--src/mesa/drivers/dri/i915/Makefile4
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.c2
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.h2
-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c8
-rw-r--r--src/mesa/drivers/dri/i915/i830_vtbl.c60
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.c2
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.h2
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c15
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c62
l---------src/mesa/drivers/dri/i915/intel_swapbuffers.c1
-rw-r--r--src/mesa/drivers/dri/i915/intel_tris.c7
11 files changed, 64 insertions, 101 deletions
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 37f15aa7671..cf32476f408 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -34,7 +34,6 @@ DRIVER_SOURCES = \
intel_pixel_read.c \
intel_buffers.c \
intel_blit.c \
- intel_swapbuffers.c \
i915_tex_layout.c \
i915_texstate.c \
i915_context.c \
@@ -64,7 +63,8 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
$(shell pkg-config libdrm --atleast-version=2.3.1 \
&& echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP")
-DRI_LIB_DEPS += -ldrm_intel
+INCLUDES += $(INTEL_CFLAGS)
+DRI_LIB_DEPS += $(INTEL_LIBS)
include ../Makefile.template
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 840946f908d..4cb63059884 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -53,7 +53,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h
index f73cbbf88bb..592ae539761 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -178,7 +178,7 @@ i830_state_draw_region(struct intel_context *intel,
*/
extern GLboolean
i830CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
/* i830_tex.c, i830_texstate.c
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index 27c5aa1e085..7525f9f2e05 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -304,10 +304,10 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
state[I830_TEXREG_TM0S4] = PACK_COLOR_8888(border[3],
border[0],
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 1e3c8301d8d..4471ca2bbbd 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -298,7 +298,7 @@ i830_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(29, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(29);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
@@ -366,7 +366,7 @@ i830_emit_invarient_state(struct intel_context *intel)
#define emit( intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size )
static GLuint
get_dirty(struct i830_hw_state *state)
@@ -429,13 +429,9 @@ i830_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -491,17 +487,14 @@ i830_emit_state(struct intel_context *intel)
}
if (dirty & I830_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
DBG("I830_UPLOAD_BUFFERS:\n");
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -523,15 +516,13 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -544,7 +535,7 @@ i830_emit_state(struct intel_context *intel)
if ((dirty & I830_UPLOAD_TEX(i))) {
DBG("I830_UPLOAD_TEX(%d):\n", i);
- BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
if (state->tex_buffer[i]) {
@@ -673,23 +664,14 @@ i830_state_draw_region(struct intel_context *intel,
}
state->Buffer[I830_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I830_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I830_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 0485be2cc1f..7c7711da099 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -100,7 +100,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[];
GLboolean
i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h
index 25418d5f7aa..f55b5511398 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -318,7 +318,7 @@ do { \
* i915_context.c
*/
extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis,
- __DRIcontextPrivate * driContextPriv,
+ __DRIcontext * driContextPriv,
void *sharedContextPrivate);
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 221bf033327..3ee4c8653a9 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -197,10 +197,11 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
state[I915_TEXREG_MS3] |= MS3_TILE_WALK;
}
- /* We get one field with fraction bits to cover the maximum addressable (smallest
- * resolution) LOD. Use it to cover both MAX_LEVEL and MAX_LOD.
+ /* We get one field with fraction bits for the maximum addressable
+ * (lowest resolution) LOD. Use it to cover both MAX_LEVEL and
+ * MAX_LOD.
*/
- maxlod = MIN2(tObj->MaxLod, tObj->MaxLevel - tObj->BaseLevel);
+ maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
state[I915_TEXREG_MS4] =
((((pitch / 4) - 1) << MS4_PITCH_SHIFT) |
MS4_CUBE_FACE_ENA_MASK |
@@ -347,10 +348,10 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
/* GL specs that border color for depth textures is taken from the
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 9f7635a9538..266e6848c3c 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -174,7 +174,7 @@ i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(17, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(17);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -220,7 +220,7 @@ i915_emit_invarient_state(struct intel_context *intel)
#define emit(intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
+ intel_batchbuffer_data(intel->batch, state, size)
static GLuint
get_dirty(struct i915_hw_state *state)
@@ -301,13 +301,9 @@ i915_emit_state(struct intel_context *intel)
* It might be better to talk about explicit places where
* scheduling is allowed, rather than assume that it is whenever a
* batchbuffer fills up.
- *
- * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
- * will be emitted under.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- LOOP_CLIPRECTS);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
aper_count = 0;
@@ -373,7 +369,7 @@ i915_emit_state(struct intel_context *intel)
}
if (dirty & I915_UPLOAD_BUFFERS) {
- GLuint count = 9;
+ GLuint count = 15;
if (INTEL_DEBUG & DEBUG_STATE)
fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
@@ -381,10 +377,7 @@ i915_emit_state(struct intel_context *intel)
if (state->depth_region)
count += 3;
- if (intel->constant_cliprect)
- count += 6;
-
- BEGIN_BATCH(count, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
@@ -406,15 +399,13 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
- if (intel->constant_cliprect) {
- assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
- }
+ assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
ADVANCE_BATCH();
}
@@ -441,7 +432,7 @@ i915_emit_state(struct intel_context *intel)
if (dirty & I915_UPLOAD_TEX(i))
nr++;
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -465,7 +456,7 @@ i915_emit_state(struct intel_context *intel)
}
ADVANCE_BATCH();
- BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(2 + nr * 3);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -623,23 +614,14 @@ i915_state_draw_region(struct intel_context *intel,
}
state->Buffer[I915_DESTREG_DV1] = value;
- if (intel->constant_cliprect) {
- state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
- state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
- state->Buffer[I915_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
- } else {
- state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
- state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
- }
+ state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
+ state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
+ state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I915_DESTREG_DRAWRECT3] =
+ (ctx->DrawBuffer->Width & 0xffff) |
+ (ctx->DrawBuffer->Height << 16);
+ state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
+ state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
}
diff --git a/src/mesa/drivers/dri/i915/intel_swapbuffers.c b/src/mesa/drivers/dri/i915/intel_swapbuffers.c
deleted file mode 120000
index 148d5215aa6..00000000000
--- a/src/mesa/drivers/dri/i915/intel_swapbuffers.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_swapbuffers.c \ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 63c5ae96dc7..e99baf8e0e6 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -89,7 +89,6 @@ intel_flush_inline_primitive(struct intel_context *intel)
static void intel_start_inline(struct intel_context *intel, uint32_t prim)
{
- uint32_t batch_flags = LOOP_CLIPRECTS;
BATCH_LOCALS;
intel->vtbl.emit_state(intel);
@@ -101,7 +100,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim)
/* Emit a slot which will be filled with the inline primitive
* command later.
*/
- BEGIN_BATCH(2, batch_flags);
+ BEGIN_BATCH(2);
OUT_BATCH(0);
assert((intel->batch->dirty_state & (1<<1)) == 0);
@@ -252,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel)
#endif
if (intel->gen >= 3) {
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
assert((offset & !S0_VB_OFFSET_MASK) == 0);
@@ -270,7 +269,7 @@ void intel_flush_prim(struct intel_context *intel)
} else {
struct i830_context *i830 = i830_context(&intel->ctx);
- BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
/* S0 */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-05 01:27:33 +0000