diff options
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs_bank_conflicts.cpp | 12 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_reg_allocate.cpp | 27 |
2 files changed, 34 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_fs_bank_conflicts.cpp b/src/intel/compiler/brw_fs_bank_conflicts.cpp index e87fcbfc5eb..938ebcceac4 100644 --- a/src/intel/compiler/brw_fs_bank_conflicts.cpp +++ b/src/intel/compiler/brw_fs_bank_conflicts.cpp @@ -540,6 +540,18 @@ namespace { for (unsigned reg = 0; reg < 2; reg++) constrained[p.atom_of_reg(reg)] = true; + /* At Intel Broadwell PRM, vol 07, section "Instruction Set Reference", + * subsection "EUISA Instructions", Send Message (page 990): + * + * "r127 must not be used for return address when there is a src and + * dest overlap in send instruction." + * + * Register allocation ensures that, so don't move 127 around to avoid + * breaking that property. + */ + if (v->devinfo->gen >= 8) + constrained[p.atom_of_reg(127)] = true; + foreach_block_and_inst(block, fs_inst, inst, v->cfg) { /* Assume that anything referenced via fixed GRFs is baked into the * hardware's fixed-function logic and may be unsafe to move around. diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index 59e047483c0..42ccb28de66 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -549,7 +549,7 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all) if (devinfo->gen >= 7) node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START; int grf127_send_hack_node = node_count; - if (devinfo->gen >= 8 && dispatch_width == 8) + if (devinfo->gen >= 8) node_count ++; struct ra_graph *g = ra_alloc_interference_graph(compiler->fs_reg_sets[rsi].regs, node_count); @@ -656,7 +656,7 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all) } } - if (devinfo->gen >= 8 && dispatch_width == 8) { + if (devinfo->gen >= 8) { /* At Intel Broadwell PRM, vol 07, section "Instruction Set Reference", * subsection "EUISA Instructions", Send Message (page 990): * @@ -671,9 +671,26 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all) * overlap between sources and destination. */ ra_set_node_reg(g, grf127_send_hack_node, 127); - foreach_block_and_inst(block, fs_inst, inst, cfg) { - if (inst->is_send_from_grf() && inst->dst.file == VGRF) { - ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node); + if (dispatch_width == 8) { + foreach_block_and_inst(block, fs_inst, inst, cfg) { + if (inst->is_send_from_grf() && inst->dst.file == VGRF) + ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node); + } + } + + if (spilled_any_registers) { + foreach_block_and_inst(block, fs_inst, inst, cfg) { + /* Spilling instruction are genereated as SEND messages from MRF + * but as Gen7+ supports sending from GRF the driver will maps + * assingn these MRF registers to a GRF. Implementations reuses + * the dest of the send message as source. So as we will have an + * overlap for sure, we create an interference between destination + * and grf127. + */ + if ((inst->opcode == SHADER_OPCODE_GEN7_SCRATCH_READ || + inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) && + inst->dst.file == VGRF) + ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node); } } } |