diff options
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/Android.common.mk | 35 | ||||
| -rw-r--r-- | src/intel/Android.mk | 1 | ||||
| -rw-r--r-- | src/intel/Makefile.am | 1 | ||||
| -rw-r--r-- | src/intel/Makefile.common.am | 24 | ||||
| -rw-r--r-- | src/intel/Makefile.isl.am | 1 | ||||
| -rw-r--r-- | src/intel/Makefile.sources | 4 | ||||
| -rw-r--r-- | src/intel/blorp/blorp_genX_exec.h | 2 | ||||
| -rw-r--r-- | src/intel/common/brw_device_info.c | 517 | ||||
| -rw-r--r-- | src/intel/common/brw_device_info.h | 147 | ||||
| -rw-r--r-- | src/intel/isl/isl_format.c | 2 | ||||
| -rw-r--r-- | src/intel/isl/isl_priv.h | 2 | ||||
| -rw-r--r-- | src/intel/isl/tests/isl_surf_get_image_offset_test.c | 2 | ||||
| -rw-r--r-- | src/intel/tools/Makefile.am | 1 | ||||
| -rw-r--r-- | src/intel/vulkan/Makefile.am | 1 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_private.h | 2 |
15 files changed, 737 insertions, 5 deletions
diff --git a/src/intel/Android.common.mk b/src/intel/Android.common.mk new file mode 100644 index 00000000000..dcc01409ff0 --- /dev/null +++ b/src/intel/Android.common.mk @@ -0,0 +1,35 @@ +# Copyright © 2016 Intel Corporation +# Copyright © 2016 Mauro Rossi <[email protected]> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# --------------------------------------- +# Build libmesa_intel_common +# --------------------------------------- + +include $(CLEAR_VARS) + +LOCAL_MODULE := libmesa_intel_common + +LOCAL_MODULE_CLASS := STATIC_LIBRARIES + +LOCAL_SRC_FILES := $(COMMON_FILES) + +include $(MESA_COMMON_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/src/intel/Android.mk b/src/intel/Android.mk index 0e9c29dfa2b..3d501abae14 100644 --- a/src/intel/Android.mk +++ b/src/intel/Android.mk @@ -26,5 +26,6 @@ LOCAL_PATH := $(call my-dir) include $(LOCAL_PATH)/Makefile.sources include $(LOCAL_PATH)/Android.blorp.mk +include $(LOCAL_PATH)/Android.common.mk include $(LOCAL_PATH)/Android.genxml.mk include $(LOCAL_PATH)/Android.isl.mk diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am index fa4570d18aa..9186b5cf1bd 100644 --- a/src/intel/Makefile.am +++ b/src/intel/Makefile.am @@ -53,6 +53,7 @@ CLEANFILES = EXTRA_DIST = include Makefile.blorp.am +include Makefile.common.am include Makefile.genxml.am include Makefile.isl.am diff --git a/src/intel/Makefile.common.am b/src/intel/Makefile.common.am new file mode 100644 index 00000000000..a8be54a265c --- /dev/null +++ b/src/intel/Makefile.common.am @@ -0,0 +1,24 @@ +# Copyright © 2016 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +noinst_LTLIBRARIES += common/libintel_common.la + +common_libintel_common_la_SOURCES = $(COMMON_FILES) diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am index 88716846cec..5a317f522bd 100644 --- a/src/intel/Makefile.isl.am +++ b/src/intel/Makefile.isl.am @@ -72,6 +72,7 @@ check_PROGRAMS += isl/tests/isl_surf_get_image_offset_test TESTS += $(check_PROGRAMS) isl_tests_isl_surf_get_image_offset_test_LDADD = \ + common/libintel_common.la \ isl/libisl.la \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ -lm diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources index fcf85eacfc4..97f2328fefe 100644 --- a/src/intel/Makefile.sources +++ b/src/intel/Makefile.sources @@ -6,6 +6,10 @@ BLORP_FILES = \ blorp/blorp_genX_exec.h \ blorp/blorp_priv.h +COMMON_FILES = \ + common/brw_device_info.c \ + common/brw_device_info.h + GENXML_GENERATED_FILES = \ genxml/gen4_pack.h \ genxml/gen45_pack.h \ diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 966e4b3da9c..461cfe0abc8 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -22,7 +22,7 @@ */ #include "blorp_priv.h" -#include "brw_device_info.h" +#include "common/brw_device_info.h" #include "intel_aub.h" /** diff --git a/src/intel/common/brw_device_info.c b/src/intel/common/brw_device_info.c new file mode 100644 index 00000000000..fb224fae234 --- /dev/null +++ b/src/intel/common/brw_device_info.c @@ -0,0 +1,517 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdlib.h> +#include "brw_device_info.h" + +static const struct brw_device_info brw_device_info_i965 = { + .gen = 4, + .has_negative_rhw_bug = true, + .num_slices = 1, + .max_vs_threads = 16, + .max_gs_threads = 2, + .max_wm_threads = 8 * 4, + .urb = { + .size = 256, + }, +}; + +static const struct brw_device_info brw_device_info_g4x = { + .gen = 4, + .has_pln = true, + .has_compr4 = true, + .has_surface_tile_offset = true, + .is_g4x = true, + .num_slices = 1, + .max_vs_threads = 32, + .max_gs_threads = 2, + .max_wm_threads = 10 * 5, + .urb = { + .size = 384, + }, +}; + +static const struct brw_device_info brw_device_info_ilk = { + .gen = 5, + .has_pln = true, + .has_compr4 = true, + .has_surface_tile_offset = true, + .num_slices = 1, + .max_vs_threads = 72, + .max_gs_threads = 32, + .max_wm_threads = 12 * 6, + .urb = { + .size = 1024, + }, +}; + +static const struct brw_device_info brw_device_info_snb_gt1 = { + .gen = 6, + .gt = 1, + .has_hiz_and_separate_stencil = true, + .has_llc = true, + .has_pln = true, + .has_surface_tile_offset = true, + .needs_unlit_centroid_workaround = true, + .num_slices = 1, + .max_vs_threads = 24, + .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */ + .max_wm_threads = 40, + .urb = { + .size = 32, + .min_vs_entries = 24, + .max_vs_entries = 256, + .max_gs_entries = 256, + }, +}; + +static const struct brw_device_info brw_device_info_snb_gt2 = { + .gen = 6, + .gt = 2, + .has_hiz_and_separate_stencil = true, + .has_llc = true, + .has_pln = true, + .has_surface_tile_offset = true, + .needs_unlit_centroid_workaround = true, + .num_slices = 1, + .max_vs_threads = 60, + .max_gs_threads = 60, + .max_wm_threads = 80, + .urb = { + .size = 64, + .min_vs_entries = 24, + .max_vs_entries = 256, + .max_gs_entries = 256, + }, +}; + +#define GEN7_FEATURES \ + .gen = 7, \ + .has_hiz_and_separate_stencil = true, \ + .must_use_separate_stencil = true, \ + .has_llc = true, \ + .has_pln = true, \ + .has_surface_tile_offset = true + +static const struct brw_device_info brw_device_info_ivb_gt1 = { + GEN7_FEATURES, .is_ivybridge = true, .gt = 1, + .num_slices = 1, + .max_vs_threads = 36, + .max_hs_threads = 36, + .max_ds_threads = 36, + .max_gs_threads = 36, + .max_wm_threads = 48, + .max_cs_threads = 36, + .urb = { + .size = 128, + .min_vs_entries = 32, + .max_vs_entries = 512, + .max_hs_entries = 32, + .min_ds_entries = 10, + .max_ds_entries = 288, + .max_gs_entries = 192, + }, +}; + +static const struct brw_device_info brw_device_info_ivb_gt2 = { + GEN7_FEATURES, .is_ivybridge = true, .gt = 2, + .num_slices = 1, + .max_vs_threads = 128, + .max_hs_threads = 128, + .max_ds_threads = 128, + .max_gs_threads = 128, + .max_wm_threads = 172, + .max_cs_threads = 64, + .urb = { + .size = 256, + .min_vs_entries = 32, + .max_vs_entries = 704, + .max_hs_entries = 64, + .min_ds_entries = 10, + .max_ds_entries = 448, + .max_gs_entries = 320, + }, +}; + +static const struct brw_device_info brw_device_info_byt = { + GEN7_FEATURES, .is_baytrail = true, .gt = 1, + .num_slices = 1, + .has_llc = false, + .max_vs_threads = 36, + .max_hs_threads = 36, + .max_ds_threads = 36, + .max_gs_threads = 36, + .max_wm_threads = 48, + .max_cs_threads = 32, + .urb = { + .size = 128, + .min_vs_entries = 32, + .max_vs_entries = 512, + .max_hs_entries = 32, + .min_ds_entries = 10, + .max_ds_entries = 288, + .max_gs_entries = 192, + }, +}; + +#define HSW_FEATURES \ + GEN7_FEATURES, \ + .is_haswell = true, \ + .supports_simd16_3src = true, \ + .has_resource_streamer = true + +static const struct brw_device_info brw_device_info_hsw_gt1 = { + HSW_FEATURES, .gt = 1, + .num_slices = 1, + .max_vs_threads = 70, + .max_hs_threads = 70, + .max_ds_threads = 70, + .max_gs_threads = 70, + .max_wm_threads = 102, + .max_cs_threads = 70, + .urb = { + .size = 128, + .min_vs_entries = 32, + .max_vs_entries = 640, + .max_hs_entries = 64, + .min_ds_entries = 10, + .max_ds_entries = 384, + .max_gs_entries = 256, + }, +}; + +static const struct brw_device_info brw_device_info_hsw_gt2 = { + HSW_FEATURES, .gt = 2, + .num_slices = 1, + .max_vs_threads = 280, + .max_hs_threads = 256, + .max_ds_threads = 280, + .max_gs_threads = 256, + .max_wm_threads = 204, + .max_cs_threads = 70, + .urb = { + .size = 256, + .min_vs_entries = 64, + .max_vs_entries = 1664, + .max_hs_entries = 128, + .min_ds_entries = 10, + .max_ds_entries = 960, + .max_gs_entries = 640, + }, +}; + +static const struct brw_device_info brw_device_info_hsw_gt3 = { + HSW_FEATURES, .gt = 3, + .num_slices = 2, + .max_vs_threads = 280, + .max_hs_threads = 256, + .max_ds_threads = 280, + .max_gs_threads = 256, + .max_wm_threads = 408, + .max_cs_threads = 70, + .urb = { + .size = 512, + .min_vs_entries = 64, + .max_vs_entries = 1664, + .max_hs_entries = 128, + .min_ds_entries = 10, + .max_ds_entries = 960, + .max_gs_entries = 640, + }, +}; + +#define GEN8_FEATURES \ + .gen = 8, \ + .has_hiz_and_separate_stencil = true, \ + .has_resource_streamer = true, \ + .must_use_separate_stencil = true, \ + .has_llc = true, \ + .has_pln = true, \ + .supports_simd16_3src = true, \ + .has_surface_tile_offset = true, \ + .max_vs_threads = 504, \ + .max_hs_threads = 504, \ + .max_ds_threads = 504, \ + .max_gs_threads = 504, \ + .max_wm_threads = 384 + +static const struct brw_device_info brw_device_info_bdw_gt1 = { + GEN8_FEATURES, .gt = 1, + .num_slices = 1, + .max_cs_threads = 42, + .urb = { + .size = 192, + .min_vs_entries = 64, + .max_vs_entries = 2560, + .max_hs_entries = 504, + .min_ds_entries = 34, + .max_ds_entries = 1536, + .max_gs_entries = 960, + } +}; + +static const struct brw_device_info brw_device_info_bdw_gt2 = { + GEN8_FEATURES, .gt = 2, + .num_slices = 1, + .max_cs_threads = 56, + .urb = { + .size = 384, + .min_vs_entries = 64, + .max_vs_entries = 2560, + .max_hs_entries = 504, + .min_ds_entries = 34, + .max_ds_entries = 1536, + .max_gs_entries = 960, + } +}; + +static const struct brw_device_info brw_device_info_bdw_gt3 = { + GEN8_FEATURES, .gt = 3, + .num_slices = 2, + .max_cs_threads = 56, + .urb = { + .size = 384, + .min_vs_entries = 64, + .max_vs_entries = 2560, + .max_hs_entries = 504, + .min_ds_entries = 34, + .max_ds_entries = 1536, + .max_gs_entries = 960, + } +}; + +static const struct brw_device_info brw_device_info_chv = { + GEN8_FEATURES, .is_cherryview = 1, .gt = 1, + .has_llc = false, + .num_slices = 1, + .max_vs_threads = 80, + .max_hs_threads = 80, + .max_ds_threads = 80, + .max_gs_threads = 80, + .max_wm_threads = 128, + .max_cs_threads = 6 * 7, + .urb = { + .size = 192, + .min_vs_entries = 34, + .max_vs_entries = 640, + .max_hs_entries = 80, + .min_ds_entries = 34, + .max_ds_entries = 384, + .max_gs_entries = 256, + } +}; + +#define GEN9_FEATURES \ + .gen = 9, \ + .has_hiz_and_separate_stencil = true, \ + .has_resource_streamer = true, \ + .must_use_separate_stencil = true, \ + .has_llc = true, \ + .has_pln = true, \ + .supports_simd16_3src = true, \ + .has_surface_tile_offset = true, \ + .max_vs_threads = 336, \ + .max_gs_threads = 336, \ + .max_hs_threads = 336, \ + .max_ds_threads = 336, \ + .max_wm_threads = 64 * 9, \ + .max_cs_threads = 56, \ + .urb = { \ + .size = 384, \ + .min_vs_entries = 64, \ + .max_vs_entries = 1856, \ + .max_hs_entries = 672, \ + .min_ds_entries = 34, \ + .max_ds_entries = 1120, \ + .max_gs_entries = 640, \ + } + +static const struct brw_device_info brw_device_info_skl_gt1 = { + GEN9_FEATURES, .gt = 1, + .num_slices = 1, + .urb.size = 192, +}; + +static const struct brw_device_info brw_device_info_skl_gt2 = { + GEN9_FEATURES, .gt = 2, + .num_slices = 1, +}; + +static const struct brw_device_info brw_device_info_skl_gt3 = { + GEN9_FEATURES, .gt = 3, + .num_slices = 2, +}; + +static const struct brw_device_info brw_device_info_skl_gt4 = { + GEN9_FEATURES, .gt = 4, + .num_slices = 3, + /* From the "L3 Allocation and Programming" documentation: + * + * "URB is limited to 1008KB due to programming restrictions. This is not a + * restriction of the L3 implementation, but of the FF and other clients. + * Therefore, in a GT4 implementation it is possible for the programmed + * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but + * only 1008KB of this will be used." + */ + .urb.size = 1008 / 3, +}; + +static const struct brw_device_info brw_device_info_bxt = { + GEN9_FEATURES, + .is_broxton = 1, + .gt = 1, + .has_llc = false, + + .num_slices = 1, + .max_vs_threads = 112, + .max_hs_threads = 112, + .max_ds_threads = 112, + .max_gs_threads = 112, + .max_wm_threads = 64 * 3, + .max_cs_threads = 6 * 6, + .urb = { + .size = 192, + .min_vs_entries = 34, + .max_vs_entries = 704, + .max_hs_entries = 256, + .max_ds_entries = 416, + .max_gs_entries = 256, + } +}; + +static const struct brw_device_info brw_device_info_bxt_2x6 = { + GEN9_FEATURES, + .is_broxton = 1, + .gt = 1, + .has_llc = false, + + .num_slices = 1, + .max_vs_threads = 56, /* XXX: guess */ + .max_hs_threads = 56, /* XXX: guess */ + .max_ds_threads = 56, + .max_gs_threads = 56, + .max_wm_threads = 64 * 2, + .max_cs_threads = 6 * 6, + .urb = { + .size = 128, + .min_vs_entries = 34, + .max_vs_entries = 352, + .max_hs_entries = 128, + .max_ds_entries = 208, + .max_gs_entries = 128, + } +}; +/* + * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+. + * There's no KBL entry. Using the default SKL (GEN9) GS entries value. + */ + +/* + * Both SKL and KBL support a maximum of 64 threads per + * Pixel Shader Dispatch (PSD) unit. + */ +#define KBL_MAX_THREADS_PER_PSD 64 + +static const struct brw_device_info brw_device_info_kbl_gt1 = { + GEN9_FEATURES, + .gt = 1, + + .max_cs_threads = 7 * 6, + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 2, + .urb.size = 192, + .num_slices = 1, +}; + +static const struct brw_device_info brw_device_info_kbl_gt1_5 = { + GEN9_FEATURES, + .gt = 1, + + .max_cs_threads = 7 * 6, + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, + .num_slices = 1, +}; + +static const struct brw_device_info brw_device_info_kbl_gt2 = { + GEN9_FEATURES, + .gt = 2, + + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, + .num_slices = 1, +}; + +static const struct brw_device_info brw_device_info_kbl_gt3 = { + GEN9_FEATURES, + .gt = 3, + + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 6, + .num_slices = 2, +}; + +static const struct brw_device_info brw_device_info_kbl_gt4 = { + GEN9_FEATURES, + .gt = 4, + + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 9, + /* + * From the "L3 Allocation and Programming" documentation: + * + * "URB is limited to 1008KB due to programming restrictions. This + * is not a restriction of the L3 implementation, but of the FF and + * other clients. Therefore, in a GT4 implementation it is + * possible for the programmed allocation of the L3 data array to + * provide 3*384KB=1152KB for URB, but only 1008KB of this + * will be used." + */ + .urb.size = 1008 / 3, + .num_slices = 3, +}; + +const struct brw_device_info * +brw_get_device_info(int devid) +{ + const struct brw_device_info *devinfo; + switch (devid) { +#undef CHIPSET +#define CHIPSET(id, family, name) \ + case id: devinfo = &brw_device_info_##family; break; +#include "pci_ids/i965_pci_ids.h" + default: + fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid); + return NULL; + } + + return devinfo; +} + +const char * +brw_get_device_name(int devid) +{ + switch (devid) { +#undef CHIPSET +#define CHIPSET(id, family, name) case id: return name; +#include "pci_ids/i965_pci_ids.h" + default: + return NULL; + } +} diff --git a/src/intel/common/brw_device_info.h b/src/intel/common/brw_device_info.h new file mode 100644 index 00000000000..0869063df32 --- /dev/null +++ b/src/intel/common/brw_device_info.h @@ -0,0 +1,147 @@ + /* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#pragma once +#include <stdbool.h> + +/** + * Intel hardware information and quirks + */ +struct brw_device_info +{ + int gen; /**< Generation number: 4, 5, 6, 7, ... */ + int gt; + + bool is_g4x; + bool is_ivybridge; + bool is_baytrail; + bool is_haswell; + bool is_cherryview; + bool is_broxton; + + bool has_hiz_and_separate_stencil; + bool must_use_separate_stencil; + + bool has_llc; + + bool has_pln; + bool has_compr4; + bool has_surface_tile_offset; + bool supports_simd16_3src; + bool has_resource_streamer; + + /** + * \name Intel hardware quirks + * @{ + */ + bool has_negative_rhw_bug; + + /** + * Some versions of Gen hardware don't do centroid interpolation correctly + * on unlit pixels, causing incorrect values for derivatives near triangle + * edges. Enabling this flag causes the fragment shader to use + * non-centroid interpolation for unlit pixels, at the expense of two extra + * fragment shader instructions. + */ + bool needs_unlit_centroid_workaround; + /** @} */ + + /** + * \name GPU hardware limits + * + * In general, you can find shader thread maximums by looking at the "Maximum + * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS, + * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry + * limits come from the "Number of URB Entries" field in the + * 3DSTATE_URB_VS command and friends. + * + * These fields are used to calculate the scratch space to allocate. The + * amount of scratch space can be larger without being harmful on modern + * GPUs, however, prior to Haswell, programming the maximum number of threads + * to greater than the hardware maximum would cause GPU performance to tank. + * + * @{ + */ + /** + * Total number of slices present on the device whether or not they've been + * fused off. + * + * XXX: CS thread counts are limited by the inability to do cross subslice + * communication. It is the effectively the number of logical threads which + * can be executed in a subslice. Fuse configurations may cause this number + * to change, so we program @max_cs_threads as the lower maximum. + */ + unsigned num_slices; + unsigned max_vs_threads; /**< Maximum Vertex Shader threads */ + unsigned max_hs_threads; /**< Maximum Hull Shader threads */ + unsigned max_ds_threads; /**< Maximum Domain Shader threads */ + unsigned max_gs_threads; /**< Maximum Geometry Shader threads. */ + /** + * Theoretical maximum number of Pixel Shader threads. + * + * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will + * automatically scale pixel shader thread count, based on a single value + * programmed into 3DSTATE_PS. + * + * To calculate the maximum number of threads for Gen8 beyond (which have + * multiple Pixel Shader Dispatchers): + * + * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD" + * - Usually there's only one PSD per subslice, so use the number of + * subslices for number of PSDs. + * - For max_wm_threads, the total should be PSD threads * #PSDs. + */ + unsigned max_wm_threads; + + /** + * Maximum Compute Shader threads. + * + * Thread count * number of EUs per subslice + */ + unsigned max_cs_threads; + + struct { + /** + * Hardware default URB size. + * + * The units this is expressed in are somewhat inconsistent: 512b units + * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+. + * + * Look up "URB Size" in the "Device Attributes" page, and take the + * maximum. Look up the slice count for each GT SKU on the same page. + * urb.size = URB Size (kbytes) / slice count + */ + unsigned size; + unsigned min_vs_entries; + unsigned max_vs_entries; + unsigned max_hs_entries; + unsigned min_ds_entries; + unsigned max_ds_entries; + unsigned max_gs_entries; + } urb; + /** @} */ +}; + +const struct brw_device_info *brw_get_device_info(int devid); +const char *brw_get_device_name(int devid); diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index 8507cc58f9a..c41a0bfcced 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -24,7 +24,7 @@ #include <assert.h> #include "isl.h" -#include "brw_device_info.h" +#include "common/brw_device_info.h" struct surface_format_info { bool exists; diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h index 9867e22a8ee..0c2ac2553fb 100644 --- a/src/intel/isl/isl_priv.h +++ b/src/intel/isl/isl_priv.h @@ -26,7 +26,7 @@ #include <assert.h> #include <strings.h> -#include "brw_device_info.h" +#include "common/brw_device_info.h" #include "util/macros.h" #include "isl.h" diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c index 9015f0e0ee4..0c9173deab4 100644 --- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c +++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -26,7 +26,7 @@ #include <stdio.h> #include <stdlib.h> -#include "brw_device_info.h" +#include "common/brw_device_info.h" #include "isl/isl.h" #include "isl/isl_priv.h" diff --git a/src/intel/tools/Makefile.am b/src/intel/tools/Makefile.am index 9f9bb869297..5f4d78d6fdc 100644 --- a/src/intel/tools/Makefile.am +++ b/src/intel/tools/Makefile.am @@ -37,6 +37,7 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/src/intel aubinator_DEPS = \ + $(top_builddir)/src/intel/common/libintel_common.la \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ $(top_builddir)/src/util/libmesautil.la \ $(PER_GEN_LIBS) \ diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am index 5491a1686e6..2d20de944d4 100644 --- a/src/intel/vulkan/Makefile.am +++ b/src/intel/vulkan/Makefile.am @@ -117,6 +117,7 @@ VULKAN_LIB_DEPS += \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ $(top_builddir)/src/compiler/nir/libnir.la \ $(top_builddir)/src/util/libmesautil.la \ + $(top_builddir)/src/intel/common/libintel_common.la \ $(top_builddir)/src/intel/isl/libisl.la \ $(PER_GEN_LIBS) \ $(PTHREAD_LIBS) \ diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index f24020cb810..74c1e5ba65f 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -40,7 +40,7 @@ #define VG(x) #endif -#include "brw_device_info.h" +#include "common/brw_device_info.h" #include "brw_compiler.h" #include "util/macros.h" #include "util/list.h" |