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-rw-r--r--src/intel/blorp/blorp_blit.c4
-rw-r--r--src/intel/blorp/blorp_clear.c4
-rw-r--r--src/intel/isl/isl.c108
-rw-r--r--src/intel/isl/isl.h38
-rw-r--r--src/intel/isl/isl_emit_depth_stencil.c6
-rw-r--r--src/intel/isl/isl_storage_image.c2
-rw-r--r--src/intel/isl/isl_surface_state.c14
-rw-r--r--src/intel/isl/tests/isl_surf_get_image_offset_test.c4
-rw-r--r--src/intel/vulkan/anv_blorp.c2
-rw-r--r--src/intel/vulkan/anv_device.c6
-rw-r--r--src/intel/vulkan/anv_image.c57
-rw-r--r--src/intel/vulkan/anv_private.h4
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c4
13 files changed, 127 insertions, 126 deletions
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 3c963c60eaf..ae3e3c50930 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2109,7 +2109,7 @@ shrink_surface_params(const struct isl_device *dev,
x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa;
y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa;
isl_tiling_get_intratile_offset_sa(info->surf.tiling,
- info->surf.format, info->surf.row_pitch,
+ info->surf.format, info->surf.row_pitch_B,
x_offset_sa, y_offset_sa,
&byte_offset,
&info->tile_x_sa, &info->tile_y_sa);
@@ -2709,7 +2709,7 @@ do_buffer_copy(struct blorp_batch *batch,
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = width * block_size,
+ .row_pitch_B = width * block_size,
.usage = ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_RENDER_TARGET_BIT,
.tiling_flags = ISL_TILING_LINEAR_BIT);
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index b4c744020d9..5b575dccc22 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -1089,7 +1089,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
isl_surf_get_image_offset_el(surf->aux_surf, level, layer, z,
&x_offset_el, &y_offset_el);
isl_tiling_get_intratile_offset_el(surf->aux_surf->tiling, aux_fmtl->bpb,
- surf->aux_surf->row_pitch,
+ surf->aux_surf->row_pitch_B,
x_offset_el, y_offset_el,
&offset_B, &x_offset_el, &y_offset_el);
params.dst.addr.offset += offset_B;
@@ -1178,7 +1178,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = surf->aux_surf->row_pitch,
+ .row_pitch_B = surf->aux_surf->row_pitch_B,
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
.tiling_flags = ISL_TILING_Y0_BIT);
assert(ok);
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f39d8a79995..359293cfcb2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1261,12 +1261,12 @@ static uint32_t
isl_calc_linear_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *info,
const struct isl_extent2d *phys_total_el,
- uint32_t alignment)
+ uint32_t alignment_B)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
const uint32_t bs = fmtl->bpb / 8;
- return isl_align_npot(bs * phys_total_el->w, alignment);
+ return isl_align_npot(bs * phys_total_el->w, alignment_B);
}
static uint32_t
@@ -1274,7 +1274,7 @@ isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
const struct isl_extent2d *phys_total_el,
- uint32_t alignment)
+ uint32_t alignment_B)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
@@ -1285,7 +1285,7 @@ isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
isl_align_div(phys_total_el->w * tile_el_scale,
tile_info->logical_extent_el.width);
- assert(alignment == tile_info->phys_extent_B.width);
+ assert(alignment_B == tile_info->phys_extent_B.width);
return total_w_tl * tile_info->phys_extent_B.width;
}
@@ -1294,14 +1294,14 @@ isl_calc_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
const struct isl_extent2d *phys_total_el,
- uint32_t alignment)
+ uint32_t alignment_B)
{
if (tile_info->tiling == ISL_TILING_LINEAR) {
return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
- alignment);
+ alignment_B);
} else {
return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
- phys_total_el, alignment);
+ phys_total_el, alignment_B);
}
}
@@ -1327,15 +1327,15 @@ isl_calc_row_pitch(const struct isl_device *dev,
const struct isl_tile_info *tile_info,
enum isl_dim_layout dim_layout,
const struct isl_extent2d *phys_total_el,
- uint32_t *out_row_pitch)
+ uint32_t *out_row_pitch_B)
{
- uint32_t alignment =
+ uint32_t alignment_B =
isl_calc_row_pitch_alignment(surf_info, tile_info);
/* If pitch isn't given and it can be chosen freely, align it by cache line
* allowing one to use blit engine on the surface.
*/
- if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) {
+ if (surf_info->row_pitch_B == 0 && tile_info->tiling == ISL_TILING_LINEAR) {
/* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
*
* "Base address of the destination surface: X=0, Y=0. Lower 32bits
@@ -1343,28 +1343,28 @@ isl_calc_row_pitch(const struct isl_device *dev,
* enabled), this address must be 4KB-aligned. When Tiling is not
* enabled, this address should be CL (64byte) aligned."
*/
- alignment = MAX2(alignment, 64);
+ alignment_B = MAX2(alignment_B, 64);
}
- const uint32_t min_row_pitch =
+ const uint32_t min_row_pitch_B =
isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
- alignment);
+ alignment_B);
- uint32_t row_pitch = min_row_pitch;
+ uint32_t row_pitch_B = min_row_pitch_B;
- if (surf_info->row_pitch != 0) {
- row_pitch = surf_info->row_pitch;
+ if (surf_info->row_pitch_B != 0) {
+ row_pitch_B = surf_info->row_pitch_B;
- if (row_pitch < min_row_pitch)
+ if (row_pitch_B < min_row_pitch_B)
return false;
- if (row_pitch % alignment != 0)
+ if (row_pitch_B % alignment_B != 0)
return false;
}
- const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width;
+ const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width;
- if (row_pitch == 0)
+ if (row_pitch_B == 0)
return false;
if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
@@ -1375,20 +1375,20 @@ isl_calc_row_pitch(const struct isl_device *dev,
if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_STORAGE_BIT)) &&
- !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
+ !pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
return false;
if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
ISL_SURF_USAGE_MCS_BIT)) &&
- !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
+ !pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
return false;
if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
- !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ !pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
return false;
if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
- !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ !pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
return false;
const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
@@ -1396,11 +1396,11 @@ isl_calc_row_pitch(const struct isl_device *dev,
_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
- !pitch_in_range(row_pitch, stencil_pitch_bits))
+ !pitch_in_range(row_pitch_B, stencil_pitch_bits))
return false;
done:
- *out_row_pitch = row_pitch;
+ *out_row_pitch_B = row_pitch_B;
return true;
}
@@ -1456,15 +1456,15 @@ isl_surf_init_s(const struct isl_device *dev,
array_pitch_span, &array_pitch_el_rows,
&phys_total_el);
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
- &phys_total_el, &row_pitch))
+ &phys_total_el, &row_pitch_B))
return false;
- uint32_t base_alignment;
- uint64_t size;
+ uint32_t base_alignment_B;
+ uint64_t size_B;
if (tiling == ISL_TILING_LINEAR) {
- size = (uint64_t) row_pitch * phys_total_el.h;
+ size_B = (uint64_t) row_pitch_B * phys_total_el.h;
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
*
@@ -1475,25 +1475,25 @@ isl_surf_init_s(const struct isl_device *dev,
* surfaces have no alignment requirements (byte alignment is
* sufficient.)"
*/
- base_alignment = MAX(1, info->min_alignment);
+ base_alignment_B = MAX(1, info->min_alignment_B);
if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
if (isl_format_is_yuv(info->format)) {
- base_alignment = MAX(base_alignment, fmtl->bpb / 4);
+ base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 4);
} else {
- base_alignment = MAX(base_alignment, fmtl->bpb / 8);
+ base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 8);
}
}
- base_alignment = isl_round_up_to_power_of_two(base_alignment);
+ base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
} else {
const uint32_t total_h_tl =
isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);
- size = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch;
+ size_B = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch_B;
- const uint32_t tile_size = tile_info.phys_extent_B.width *
- tile_info.phys_extent_B.height;
- assert(isl_is_pow2(info->min_alignment) && isl_is_pow2(tile_size));
- base_alignment = MAX(info->min_alignment, tile_size);
+ const uint32_t tile_size_B = tile_info.phys_extent_B.width *
+ tile_info.phys_extent_B.height;
+ assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B));
+ base_alignment_B = MAX(info->min_alignment_B, tile_size_B);
}
if (ISL_DEV_GEN(dev) < 9) {
@@ -1505,7 +1505,7 @@ isl_surf_init_s(const struct isl_device *dev,
*
* This comment is applicable to all Pre-gen9 platforms.
*/
- if (size > (uint64_t) 1 << 31)
+ if (size_B > (uint64_t) 1 << 31)
return false;
} else if (ISL_DEV_GEN(dev) < 11) {
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
@@ -1514,11 +1514,11 @@ isl_surf_init_s(const struct isl_device *dev,
* All pixels within the surface must be contained within 2^38 bytes
* of the base address."
*/
- if (size > (uint64_t) 1 << 38)
+ if (size_B > (uint64_t) 1 << 38)
return false;
} else {
/* gen11+ platforms raised this limit to 2^44 bytes. */
- if (size > (uint64_t) 1 << 44)
+ if (size_B > (uint64_t) 1 << 44)
return false;
}
@@ -1536,9 +1536,9 @@ isl_surf_init_s(const struct isl_device *dev,
.logical_level0_px = logical_level0_px,
.phys_level0_sa = phys_level0_sa,
- .size = size,
- .alignment = base_alignment,
- .row_pitch = row_pitch,
+ .size_B = size_B,
+ .alignment_B = base_alignment_B,
+ .row_pitch_B = row_pitch_B,
.array_pitch_el_rows = array_pitch_el_rows,
.array_pitch_span = array_pitch_span,
@@ -1689,7 +1689,7 @@ bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *ccs_surf,
- uint32_t row_pitch)
+ uint32_t row_pitch_B)
{
assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(ISL_DEV_GEN(dev) >= 7);
@@ -1767,7 +1767,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
.levels = surf->levels,
.array_len = surf->logical_level0_px.array_len,
.samples = 1,
- .row_pitch = row_pitch,
+ .row_pitch_B = row_pitch_B,
.usage = ISL_SURF_USAGE_CCS_BIT,
.tiling_flags = ISL_TILING_CCS_BIT);
}
@@ -2171,7 +2171,7 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
uint32_t x_offset_el, y_offset_el;
isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
- surf->row_pitch,
+ surf->row_pitch_B,
total_x_offset_el,
total_y_offset_el,
offset_B,
@@ -2226,7 +2226,7 @@ isl_surf_get_image_surf(const struct isl_device *dev,
.levels = 1,
.array_len = 1,
.samples = surf->samples,
- .row_pitch = surf->row_pitch,
+ .row_pitch_B = surf->row_pitch_B,
.usage = usage,
.tiling_flags = (1 << surf->tiling));
assert(ok);
@@ -2235,7 +2235,7 @@ isl_surf_get_image_surf(const struct isl_device *dev,
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t bpb,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
@@ -2244,7 +2244,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
{
if (tiling == ISL_TILING_LINEAR) {
assert(bpb % 8 == 0);
- *base_address_offset = total_y_offset_el * row_pitch +
+ *base_address_offset = total_y_offset_el * row_pitch_B +
total_x_offset_el * (bpb / 8);
*x_offset_el = 0;
*y_offset_el = 0;
@@ -2254,7 +2254,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
struct isl_tile_info tile_info;
isl_tiling_get_info(tiling, bpb, &tile_info);
- assert(row_pitch % tile_info.phys_extent_B.width == 0);
+ assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
/* For non-power-of-two formats, we need the address to be both tile and
* element-aligned. The easiest way to achieve this is to work with a tile
@@ -2277,7 +2277,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
*base_address_offset =
- y_offset_tl * tile_info.phys_extent_B.h * row_pitch +
+ y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
}
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 6800b1d76a6..d53c69adbde 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1085,7 +1085,7 @@ struct isl_tile_info {
* always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
* its physical size is 128B x 32rows, the same as a Y-tile.
*
- * @see isl_surf::row_pitch
+ * @see isl_surf::row_pitch_B
*/
struct isl_extent2d phys_extent_B;
};
@@ -1135,13 +1135,13 @@ struct isl_surf_init_info {
uint32_t samples;
/** Lower bound for isl_surf::alignment, in bytes. */
- uint32_t min_alignment;
+ uint32_t min_alignment_B;
/**
* Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
* will fail if this is misaligned or out of bounds.
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
isl_surf_usage_flags_t usage;
@@ -1184,17 +1184,17 @@ struct isl_surf {
uint32_t samples;
/** Total size of the surface, in bytes. */
- uint64_t size;
+ uint64_t size_B;
/** Required alignment for the surface's base address. */
- uint32_t alignment;
+ uint32_t alignment_B;
/**
* The interpretation of this field depends on the value of
* isl_tile_info::physical_extent_B. In particular, the width of the
- * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
+ * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
* and the distance in bytes between vertically adjacent tiles in the image
- * is given by row_pitch * isl_tile_info::physical_extent_B.height.
+ * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
*
* For linear images where isl_tile_info::physical_extent_B.height == 1,
* this cleanly reduces to being the distance, in bytes, between vertically
@@ -1202,7 +1202,7 @@ struct isl_surf {
*
* @see isl_tile_info::phys_extent_B;
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
/**
* Pitch between physical array slices, in rows of surface elements.
@@ -1338,7 +1338,7 @@ struct isl_buffer_fill_state_info {
/**
* The size of the buffer
*/
- uint64_t size;
+ uint64_t size_B;
/**
* The Memory Object Control state for the filled surface state.
@@ -1355,7 +1355,7 @@ struct isl_buffer_fill_state_info {
*/
enum isl_format format;
- uint32_t stride;
+ uint32_t stride_B;
};
struct isl_depth_stencil_hiz_emit_info {
@@ -1805,7 +1805,7 @@ bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *ccs_surf,
- uint32_t row_pitch /**< Ignored if 0 */);
+ uint32_t row_pitch_B /**< Ignored if 0 */);
#define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
@@ -1875,9 +1875,9 @@ isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
* Pitch between vertically adjacent surface elements, in bytes.
*/
static inline uint32_t
-isl_surf_get_row_pitch(const struct isl_surf *surf)
+isl_surf_get_row_pitch_B(const struct isl_surf *surf)
{
- return surf->row_pitch;
+ return surf->row_pitch_B;
}
/**
@@ -1888,8 +1888,8 @@ isl_surf_get_row_pitch_el(const struct isl_surf *surf)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
- return surf->row_pitch / (fmtl->bpb / 8);
+ assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
+ return surf->row_pitch_B / (fmtl->bpb / 8);
}
/**
@@ -1927,7 +1927,7 @@ isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf *surf)
{
- return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
+ return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
}
/**
@@ -2019,7 +2019,7 @@ isl_surf_get_image_surf(const struct isl_device *dev,
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t bpb,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
@@ -2029,7 +2029,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
enum isl_format format,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_sa,
uint32_t total_y_offset_sa,
uint32_t *base_address_offset,
@@ -2047,7 +2047,7 @@ isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
- isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
+ isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
total_x_offset, total_y_offset,
base_address_offset,
x_offset_sa, y_offset_sa);
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 51b3f005c01..9cf5a476687 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -104,7 +104,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
#endif
- db.SurfacePitch = info->depth_surf->row_pitch - 1;
+ db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
#if GEN_GEN >= 8
db.SurfaceQPitch =
isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
@@ -140,7 +140,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
#if GEN_GEN >= 6
sb.StencilBufferMOCS = info->mocs;
#endif
- sb.SurfacePitch = info->stencil_surf->row_pitch - 1;
+ sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
#if GEN_GEN >= 8
sb.SurfaceQPitch =
isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
@@ -162,7 +162,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
hiz.SurfaceBaseAddress = info->hiz_address;
hiz.HierarchicalDepthBufferMOCS = info->mocs;
- hiz.SurfacePitch = info->hiz_surf->row_pitch - 1;
+ hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
#if GEN_GEN >= 8
/* From the SKL PRM Vol2a:
*
diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c
index c36985af127..f8bb5275358 100644
--- a/src/intel/isl/isl_storage_image.c
+++ b/src/intel/isl/isl_storage_image.c
@@ -249,7 +249,7 @@ isl_surf_fill_image_param(const struct isl_device *dev,
const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
param->stride[0] = cpp;
- param->stride[1] = surf->row_pitch / cpp;
+ param->stride[1] = surf->row_pitch_B / cpp;
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index f181c3dfb2f..7ab260d701b 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -430,7 +430,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
/* For gen9 1-D textures, surface pitch is ignored */
s.SurfacePitch = 0;
} else {
- s.SurfacePitch = info->surf->row_pitch - 1;
+ s.SurfacePitch = info->surf->row_pitch_B - 1;
}
#if GEN_GEN >= 8
@@ -536,7 +536,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
struct isl_tile_info tile_info;
isl_surf_get_tile_info(info->aux_surf, &tile_info);
uint32_t pitch_in_tiles =
- info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
+ info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
s.AuxiliarySurfaceBaseAddress = info->aux_address;
s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
@@ -658,7 +658,7 @@ void
isl_genX(buffer_fill_state_s)(void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
- uint64_t buffer_size = info->size;
+ uint64_t buffer_size = info->size_B;
/* Uniform and Storage buffers need to have surface size not less that the
* aligned 32-bit size of the buffer. To calculate the array lenght on
@@ -672,13 +672,13 @@ isl_genX(buffer_fill_state_s)(void *state,
* buffer_size = (surface_size & ~3) - (surface_size & 3)
*/
if (info->format == ISL_FORMAT_RAW ||
- info->stride < isl_format_get_layout(info->format)->bpb / 8) {
- assert(info->stride == 1);
+ info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
+ assert(info->stride_B == 1);
uint64_t aligned_size = isl_align(buffer_size, 4);
buffer_size = aligned_size + (aligned_size - buffer_size);
}
- uint32_t num_elements = buffer_size / info->stride;
+ uint32_t num_elements = buffer_size / info->stride_B;
if (GEN_GEN >= 7) {
/* From the IVB PRM, SURFACE_STATE::Height,
@@ -721,7 +721,7 @@ isl_genX(buffer_fill_state_s)(void *state,
s.Depth = ((num_elements - 1) >> 20) & 0x7f;
#endif
- s.SurfacePitch = info->stride - 1;
+ s.SurfacePitch = info->stride_B - 1;
#if GEN_GEN >= 6
s.NumberofMultisamples = MULTISAMPLECOUNT_1;
diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
index 16c80c312e9..703f176c6b3 100644
--- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c
+++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
@@ -153,7 +153,7 @@ test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void)
isl_surf_get_array_pitch_sa_rows(&surf));
/* Row pitch should be minimal possible */
- t_assert(surf.row_pitch == 2048);
+ t_assert(surf.row_pitch_B == 2048);
t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0
t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512
@@ -201,7 +201,7 @@ test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void)
isl_surf_get_array_pitch_sa_rows(&surf));
/* Row pitch should be minimal possible */
- t_assert(surf.row_pitch == 4096);
+ t_assert(surf.row_pitch_B == 4096);
for (uint32_t a = 0; a < 6; ++a) {
uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf);
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 9ab291eabec..a1c359cf461 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -168,7 +168,7 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = row_pitch,
+ .row_pitch_B = row_pitch,
.usage = ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_RENDER_TARGET_BIT,
.tiling_flags = ISL_TILING_LINEAR_BIT);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4219a073d2d..2286df6331a 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2279,7 +2279,7 @@ VkResult anv_AllocateMemory(
const uint32_t i915_tiling =
isl_tiling_to_i915_tiling(image->planes[0].surface.isl.tiling);
int ret = anv_gem_set_tiling(device, mem->bo->gem_handle,
- image->planes[0].surface.isl.row_pitch,
+ image->planes[0].surface.isl.row_pitch_B,
i915_tiling);
if (ret) {
anv_bo_cache_release(device, &device->bo_cache, mem->bo);
@@ -2897,9 +2897,9 @@ anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state state,
isl_buffer_fill_state(&device->isl_dev, state.map,
.address = anv_address_physical(address),
.mocs = device->default_mocs,
- .size = range,
+ .size_B = range,
.format = format,
- .stride = stride);
+ .stride_B = stride);
anv_state_flush(device, state);
}
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index a3aecb93901..b0d8c560adb 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -135,24 +135,25 @@ get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
static void
add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
{
- assert(surf->isl.size > 0); /* isl surface must be initialized */
+ assert(surf->isl.size_B > 0); /* isl surface must be initialized */
if (image->disjoint) {
- surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment);
+ surf->offset = align_u32(image->planes[plane].size,
+ surf->isl.alignment_B);
/* Plane offset is always 0 when it's disjoint. */
} else {
- surf->offset = align_u32(image->size, surf->isl.alignment);
+ surf->offset = align_u32(image->size, surf->isl.alignment_B);
/* Determine plane's offset only once when the first surface is added. */
if (image->planes[plane].size == 0)
image->planes[plane].offset = image->size;
}
- image->size = surf->offset + surf->isl.size;
- image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset;
+ image->size = surf->offset + surf->isl.size_B;
+ image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
- image->alignment = MAX2(image->alignment, surf->isl.alignment);
+ image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
- surf->isl.alignment);
+ surf->isl.alignment_B);
}
@@ -249,7 +250,7 @@ add_aux_state_tracking_buffer(struct anv_image *image,
const struct anv_device *device)
{
assert(image && device);
- assert(image->planes[plane].aux_surface.isl.size > 0 &&
+ assert(image->planes[plane].aux_surface.isl.size_B > 0 &&
image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
/* Compressed images must be tiled and therefore everything should be 4K
@@ -348,8 +349,8 @@ make_surface(const struct anv_device *dev,
.levels = vk_info->mipLevels,
.array_len = vk_info->arrayLayers,
.samples = vk_info->samples,
- .min_alignment = 0,
- .row_pitch = anv_info->stride,
+ .min_alignment_B = 0,
+ .row_pitch_B = anv_info->stride,
.usage = usage,
.tiling_flags = tiling_flags);
@@ -377,8 +378,8 @@ make_surface(const struct anv_device *dev,
.levels = vk_info->mipLevels,
.array_len = vk_info->arrayLayers,
.samples = vk_info->samples,
- .min_alignment = 0,
- .row_pitch = anv_info->stride,
+ .min_alignment_B = 0,
+ .row_pitch_B = anv_info->stride,
.usage = usage,
.tiling_flags = ISL_TILING_ANY_MASK);
@@ -413,7 +414,7 @@ make_surface(const struct anv_device *dev,
} else if (dev->info.gen == 8 && vk_info->samples > 1) {
anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ");
} else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_hiz_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl);
@@ -439,7 +440,7 @@ make_surface(const struct anv_device *dev,
likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
if (allow_compression) {
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_ccs_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl, 0);
@@ -457,7 +458,7 @@ make_surface(const struct anv_device *dev,
anv_perf_warn(dev->instance, image,
"This image format doesn't support rendering. "
"Not allocating an CCS buffer.");
- image->planes[plane].aux_surface.isl.size = 0;
+ image->planes[plane].aux_surface.isl.size_B = 0;
return VK_SUCCESS;
}
@@ -480,7 +481,7 @@ make_surface(const struct anv_device *dev,
}
} else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) {
assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_mcs_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl);
@@ -498,14 +499,14 @@ make_surface(const struct anv_device *dev,
*/
assert((MAX2(image->planes[plane].surface.offset,
image->planes[plane].aux_surface.offset) +
- (image->planes[plane].aux_surface.isl.size > 0 ?
- image->planes[plane].aux_surface.isl.size :
- image->planes[plane].surface.isl.size)) <=
+ (image->planes[plane].aux_surface.isl.size_B > 0 ?
+ image->planes[plane].aux_surface.isl.size_B :
+ image->planes[plane].surface.isl.size_B)) <=
(image->planes[plane].offset + image->planes[plane].size));
- if (image->planes[plane].aux_surface.isl.size) {
+ if (image->planes[plane].aux_surface.isl.size_B) {
/* assert(image->planes[plane].fast_clear_state_offset == */
- /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
+ /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
assert(image->planes[plane].fast_clear_state_offset <
(image->planes[plane].offset + image->planes[plane].size));
}
@@ -766,7 +767,7 @@ void anv_GetImageSubresourceLayout(
assert(__builtin_popcount(subresource->aspectMask) == 1);
layout->offset = surface->offset;
- layout->rowPitch = surface->isl.row_pitch;
+ layout->rowPitch = surface->isl.row_pitch_B;
layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
@@ -783,7 +784,7 @@ void anv_GetImageSubresourceLayout(
layout->size = layout->rowPitch * anv_minify(image->extent.height,
subresource->mipLevel);
} else {
- layout->size = surface->isl.size;
+ layout->size = surface->isl.size_B;
}
}
@@ -824,7 +825,7 @@ anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
/* If there is no auxiliary surface allocated, we must use the one and only
* main buffer.
*/
- if (image->planes[plane].aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
return ISL_AUX_USAGE_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
@@ -948,7 +949,7 @@ anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
/* If there is no auxiliary surface allocated, there are no fast-clears */
- if (image->planes[plane].aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
return ANV_FAST_CLEAR_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
@@ -1058,7 +1059,7 @@ anv_image_fill_surface_state(struct anv_device *device,
* the primary surface. The shadow surface will be tiled, unlike the main
* surface, so it should get significantly better performance.
*/
- if (image->planes[plane].shadow_surface.isl.size > 0 &&
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
isl_format_is_compressed(view.format) &&
(flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
assert(isl_format_is_compressed(surface->isl.format));
@@ -1093,9 +1094,9 @@ anv_image_fill_surface_state(struct anv_device *device,
assert(aux_usage == ISL_AUX_USAGE_NONE);
isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
.address = anv_address_physical(address),
- .size = surface->isl.size,
+ .size_B = surface->isl.size_B,
.format = ISL_FORMAT_RAW,
- .stride = 1,
+ .stride_B = 1,
.mocs = device->default_mocs);
state_inout->address = address,
state_inout->aux_address = ANV_NULL_ADDRESS;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d15a91dd014..60f40c7e2ae 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2615,7 +2615,7 @@ anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
* Subsurface of an anv_image.
*/
struct anv_surface {
- /** Valid only if isl_surf::size > 0. */
+ /** Valid only if isl_surf::size_B > 0. */
struct isl_surf isl;
/**
@@ -2764,7 +2764,7 @@ anv_image_aux_levels(const struct anv_image * const image,
VkImageAspectFlagBits aspect)
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- return image->planes[plane].aux_surface.isl.size > 0 ?
+ return image->planes[plane].aux_surface.isl.size_B > 0 ?
image->planes[plane].aux_surface.isl.levels : 0;
}
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a9a8a41ac9d..099c30f3d66 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -948,7 +948,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- if (image->planes[plane].shadow_surface.isl.size > 0 &&
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
/* This surface is a linear compressed image with a tiled shadow surface
* for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
@@ -3760,7 +3760,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
if (GEN_GEN < 10 &&
(att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
- image->planes[0].aux_surface.isl.size > 0 &&
+ image->planes[0].aux_surface.isl.size_B > 0 &&
iview->planes[0].isl.base_level == 0 &&
iview->planes[0].isl.base_array_layer == 0) {
if (att_state->aux_usage != ISL_AUX_USAGE_NONE) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 11:05:30 +0000