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-rw-r--r--src/intel/vulkan/anv_descriptor_set.c11
-rw-r--r--src/intel/vulkan/anv_nir_apply_pipeline_layout.c17
-rw-r--r--src/intel/vulkan/anv_pipeline_cache.c4
-rw-r--r--src/intel/vulkan/anv_private.h6
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c14
5 files changed, 29 insertions, 23 deletions
diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c
index 6b3a40f7b1c..a31cc84bb52 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -150,7 +150,7 @@ VkResult anv_CreateDescriptorSetLayout(
uint32_t sampler_count[MESA_SHADER_STAGES] = { 0, };
uint32_t surface_count[MESA_SHADER_STAGES] = { 0, };
- uint32_t image_count[MESA_SHADER_STAGES] = { 0, };
+ uint32_t image_param_count[MESA_SHADER_STAGES] = { 0, };
uint32_t buffer_view_count = 0;
uint32_t dynamic_offset_count = 0;
@@ -245,9 +245,12 @@ VkResult anv_CreateDescriptorSetLayout(
switch (binding->descriptorType) {
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
- anv_foreach_stage(s, binding->stageFlags) {
- set_layout->binding[b].stage[s].image_index = image_count[s];
- image_count[s] += binding->descriptorCount;
+ if (device->info.gen < 9) {
+ anv_foreach_stage(s, binding->stageFlags) {
+ set_layout->binding[b].stage[s].image_param_index =
+ image_param_count[s];
+ image_param_count[s] += binding->descriptorCount;
+ }
}
break;
default:
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 623984b0f8c..889d58aa84c 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -521,23 +521,23 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
}
}
- if (binding->stage[stage].image_index >= 0) {
- state.set[set].image_offsets[b] = map->image_count;
- map->image_count += binding->array_size;
+ if (binding->stage[stage].image_param_index >= 0) {
+ state.set[set].image_offsets[b] = map->image_param_count;
+ map->image_param_count += binding->array_size;
}
}
}
- if (map->image_count > 0 && pdevice->compiler->devinfo->gen < 9) {
- assert(map->image_count <= MAX_GEN8_IMAGES);
+ if (map->image_param_count > 0) {
+ assert(map->image_param_count <= MAX_GEN8_IMAGES);
assert(shader->num_uniforms == prog_data->nr_params * 4);
state.first_image_uniform = shader->num_uniforms;
uint32_t *param = brw_stage_prog_data_add_params(prog_data,
- map->image_count *
+ map->image_param_count *
BRW_IMAGE_PARAM_SIZE);
struct anv_push_constants *null_data = NULL;
const struct brw_image_param *image_param = null_data->images;
- for (uint32_t i = 0; i < map->image_count; i++) {
+ for (uint32_t i = 0; i < map->image_param_count; i++) {
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
(uintptr_t)image_param->offset, 2);
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
@@ -554,7 +554,8 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
}
assert(param == prog_data->param + prog_data->nr_params);
- shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
+ shader->num_uniforms += map->image_param_count *
+ BRW_IMAGE_PARAM_SIZE * 4;
assert(shader->num_uniforms == prog_data->nr_params * 4);
}
diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c
index ad1bcf0940f..056e2df6e9a 100644
--- a/src/intel/vulkan/anv_pipeline_cache.c
+++ b/src/intel/vulkan/anv_pipeline_cache.c
@@ -154,7 +154,7 @@ anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
blob_write_uint32(blob, shader->bind_map.surface_count);
blob_write_uint32(blob, shader->bind_map.sampler_count);
- blob_write_uint32(blob, shader->bind_map.image_count);
+ blob_write_uint32(blob, shader->bind_map.image_param_count);
blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
shader->bind_map.surface_count *
sizeof(*shader->bind_map.surface_to_descriptor));
@@ -194,7 +194,7 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
struct anv_pipeline_bind_map bind_map;
bind_map.surface_count = blob_read_uint32(blob);
bind_map.sampler_count = blob_read_uint32(blob);
- bind_map.image_count = blob_read_uint32(blob);
+ bind_map.image_param_count = blob_read_uint32(blob);
bind_map.surface_to_descriptor = (void *)
blob_read_bytes(blob, bind_map.surface_count *
sizeof(*bind_map.surface_to_descriptor));
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index e6750cada2a..f00061c711d 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1523,8 +1523,8 @@ struct anv_descriptor_set_binding_layout {
/* Index into the sampler table for the associated sampler */
int16_t sampler_index;
- /* Index into the image table for the associated image */
- int16_t image_index;
+ /* Index into the image param table for the associated image */
+ int16_t image_param_index;
} stage[MESA_SHADER_STAGES];
/* Immutable samplers (or NULL if no immutable samplers) */
@@ -2535,7 +2535,7 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
struct anv_pipeline_bind_map {
uint32_t surface_count;
uint32_t sampler_count;
- uint32_t image_count;
+ uint32_t image_param_count;
struct anv_pipeline_binding * surface_to_descriptor;
struct anv_pipeline_binding * sampler_to_descriptor;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a7e63a6db83..b5fc8be9475 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2070,7 +2070,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
/* We only use push constant space for images before gen9 */
- if (map->image_count > 0 && devinfo->gen < 9) {
+ if (map->image_param_count > 0) {
VkResult result =
anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
if (result != VK_SUCCESS)
@@ -2203,14 +2203,17 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
assert(surface_state.alloc_size);
add_surface_state_relocs(cmd_buffer, sstate);
if (devinfo->gen < 9) {
+ /* We only need the image params on gen8 and earlier. No image
+ * workarounds that require tiling information are required on
+ * SKL and above.
+ */
assert(image < MAX_GEN8_IMAGES);
struct brw_image_param *image_param =
- &cmd_buffer->state.push_constants[stage]->images[image];
+ &cmd_buffer->state.push_constants[stage]->images[image++];
*image_param =
desc->image_view->planes[binding->plane].storage_image_param;
}
- image++;
break;
}
@@ -2258,11 +2261,10 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
if (devinfo->gen < 9) {
assert(image < MAX_GEN8_IMAGES);
struct brw_image_param *image_param =
- &cmd_buffer->state.push_constants[stage]->images[image];
+ &cmd_buffer->state.push_constants[stage]->images[image++];
*image_param = desc->buffer_view->storage_image_param;
}
- image++;
break;
default:
@@ -2272,7 +2274,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
bt_map[s] = surface_state.offset + state_offset;
}
- assert(image == map->image_count);
+ assert(image == map->image_param_count);
#if GEN_GEN >= 11
/* The PIPE_CONTROL command description says:
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 23:44:31 +0000