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-rw-r--r--src/intel/genxml/gen6.xml8
-rw-r--r--src/intel/genxml/gen7.xml8
-rw-r--r--src/intel/genxml/gen75.xml8
-rw-r--r--src/intel/vulkan/gen7_pipeline.c25
4 files changed, 34 insertions, 15 deletions
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 44e28048ac5..dd682dda660 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -79,7 +79,7 @@
</group>
</struct>
- <struct name="BLEND_STATE" length="2">
+ <struct name="BLEND_STATE_ENTRY" length="2">
<field name="Color Buffer Blend Enable" start="31" end="31" type="bool"/>
<field name="Independent Alpha Blend Enable" start="30" end="30" type="bool"/>
<field name="Alpha Blend Function" start="26" end="28" type="uint">
@@ -169,6 +169,12 @@
<field name="Post-Blend Color Clamp Enable" start="32" end="32" type="bool"/>
</struct>
+ <struct name="BLEND_STATE" length="16">
+ <group count="8" start="0" size="64">
+ <field name="Entry" start="0" end="63" type="BLEND_STATE_ENTRY"/>
+ </group>
+ </struct>
+
<struct name="CC_VIEWPORT" length="2">
<field name="Minimum Depth" start="0" end="31" type="float"/>
<field name="Maximum Depth" start="32" end="63" type="float"/>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 2bbfcb7606a..15640011626 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -102,7 +102,7 @@
</group>
</struct>
- <struct name="BLEND_STATE" length="2">
+ <struct name="BLEND_STATE_ENTRY" length="2">
<field name="Color Buffer Blend Enable" start="31" end="31" type="bool"/>
<field name="Independent Alpha Blend Enable" start="30" end="30" type="bool"/>
<field name="Alpha Blend Function" start="26" end="28" type="uint">
@@ -192,6 +192,12 @@
<field name="Post-Blend Color Clamp Enable" start="32" end="32" type="bool"/>
</struct>
+ <struct name="BLEND_STATE" length="16">
+ <group count="8" start="0" size="64">
+ <field name="Entry" start="0" end="63" type="BLEND_STATE_ENTRY"/>
+ </group>
+ </struct>
+
<struct name="CC_VIEWPORT" length="2">
<field name="Minimum Depth" start="0" end="31" type="float"/>
<field name="Maximum Depth" start="32" end="63" type="float"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9ab432cacb0..d813b7b7be2 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -112,7 +112,7 @@
</group>
</struct>
- <struct name="BLEND_STATE" length="2">
+ <struct name="BLEND_STATE_ENTRY" length="2">
<field name="Color Buffer Blend Enable" start="31" end="31" type="bool"/>
<field name="Independent Alpha Blend Enable" start="30" end="30" type="bool"/>
<field name="Alpha Blend Function" start="26" end="28" type="uint">
@@ -202,6 +202,12 @@
<field name="Post-Blend Color Clamp Enable" start="32" end="32" type="bool"/>
</struct>
+ <struct name="BLEND_STATE" length="16">
+ <group count="8" start="0" size="64">
+ <field name="Entry" start="0" end="63" type="BLEND_STATE_ENTRY"/>
+ </group>
+ </struct>
+
<struct name="CC_VIEWPORT" length="2">
<field name="Minimum Depth" start="0" end="31" type="float"/>
<field name="Maximum Depth" start="32" end="63" type="float"/>
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 89cb51f8916..dba24e78ac1 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -86,17 +86,18 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
pipeline->blend_state =
anv_state_pool_emit(&device->dynamic_state_pool,
GENX(BLEND_STATE), 64,
- .ColorBufferBlendEnable = false,
- .WriteDisableAlpha = true,
- .WriteDisableRed = true,
- .WriteDisableGreen = true,
- .WriteDisableBlue = true);
+ .Entry = { {
+ .ColorBufferBlendEnable = false,
+ .WriteDisableAlpha = true,
+ .WriteDisableRed = true,
+ .WriteDisableGreen = true,
+ .WriteDisableBlue = true
+ } });
} else {
const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
- struct GENX(BLEND_STATE) blend = {
+ struct GENX(BLEND_STATE) blend = { .Entry = { {
.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
-
.LogicOpEnable = info->logicOpEnable,
.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
.ColorBufferBlendEnable = a->blendEnable,
@@ -113,7 +114,7 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
- };
+ } } };
/* Our hardware applies the blend factor prior to the blend function
* regardless of what function is used. Technically, this means the
@@ -123,13 +124,13 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
*/
if (a->colorBlendOp == VK_BLEND_OP_MIN ||
a->colorBlendOp == VK_BLEND_OP_MAX) {
- blend.SourceBlendFactor = BLENDFACTOR_ONE;
- blend.DestinationBlendFactor = BLENDFACTOR_ONE;
+ blend.Entry[0].SourceBlendFactor = BLENDFACTOR_ONE;
+ blend.Entry[0].DestinationBlendFactor = BLENDFACTOR_ONE;
}
if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
a->alphaBlendOp == VK_BLEND_OP_MAX) {
- blend.SourceAlphaBlendFactor = BLENDFACTOR_ONE;
- blend.DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
+ blend.Entry[0].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
+ blend.Entry[0].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
}
pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 17:38:45 +0000