diff options
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 8 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_generator.cpp | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 0c85eb8e1e0..6d5306a0eee 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -740,7 +740,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload) } void -fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src) +fs_generator::generate_barrier(fs_inst *, struct brw_reg src) { brw_barrier(p, src); brw_WAIT(p); @@ -1323,7 +1323,7 @@ fs_generator::generate_ddy(const fs_inst *inst, } void -fs_generator::generate_discard_jump(fs_inst *inst) +fs_generator::generate_discard_jump(fs_inst *) { assert(devinfo->gen >= 6); @@ -1672,7 +1672,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst, } void -fs_generator::generate_pack_half_2x16_split(fs_inst *inst, +fs_generator::generate_pack_half_2x16_split(fs_inst *, struct brw_reg dst, struct brw_reg x, struct brw_reg y) @@ -1740,7 +1740,7 @@ fs_generator::generate_unpack_half_2x16_split(fs_inst *inst, } void -fs_generator::generate_shader_time_add(fs_inst *inst, +fs_generator::generate_shader_time_add(fs_inst *, struct brw_reg payload, struct brw_reg offset, struct brw_reg value) diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index a3ed8609a29..3d17ff97971 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1409,7 +1409,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p, static void generate_set_simd4x2_header_gen9(struct brw_codegen *p, - vec4_instruction *inst, + vec4_instruction *, struct brw_reg dst) { brw_push_insn_state(p); @@ -1427,9 +1427,9 @@ generate_set_simd4x2_header_gen9(struct brw_codegen *p, static void generate_mov_indirect(struct brw_codegen *p, - vec4_instruction *inst, + vec4_instruction *, struct brw_reg dst, struct brw_reg reg, - struct brw_reg indirect, struct brw_reg length) + struct brw_reg indirect) { assert(indirect.type == BRW_REGISTER_TYPE_UD); assert(p->devinfo->gen >= 6); @@ -2141,7 +2141,7 @@ generate_code(struct brw_codegen *p, break; case SHADER_OPCODE_MOV_INDIRECT: - generate_mov_indirect(p, inst, dst, src[0], src[1], src[2]); + generate_mov_indirect(p, inst, dst, src[0], src[1]); break; case BRW_OPCODE_DIM: |