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-rw-r--r--src/intel/blorp/blorp_blit.c18
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp35
-rw-r--r--src/intel/compiler/brw_nir_attribute_workarounds.c10
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp67
-rw-r--r--src/intel/vulkan/anv_nir_lower_input_attachments.c2
5 files changed, 55 insertions, 77 deletions
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 0cc5a840338..e650d5e7bf1 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -97,7 +97,7 @@ blorp_blit_get_frag_coords(nir_builder *b,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
{
- nir_ssa_def *coord = nir_f2i(b, nir_load_var(b, v->frag_coord));
+ nir_ssa_def *coord = nir_f2i32(b, nir_load_var(b, v->frag_coord));
/* Account for destination surface intratile offset
*
@@ -764,7 +764,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
nir_ssa_def *sample_off = nir_imm_vec2(b, sample_off_x, sample_off_y);
nir_ssa_def *sample_coords = nir_fadd(b, pos_xy, sample_off);
- nir_ssa_def *sample_coords_int = nir_f2i(b, sample_coords);
+ nir_ssa_def *sample_coords_int = nir_f2i32(b, sample_coords);
/* The MCS value we fetch has to match up with the pixel that we're
* sampling from. Since we sample from different pixels in each
@@ -821,7 +821,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
nir_ssa_def *sample =
nir_fdot2(b, frac, nir_imm_vec2(b, key->x_scale,
key->x_scale * key->y_scale));
- sample = nir_f2i(b, sample);
+ sample = nir_f2i32(b, sample);
if (tex_samples == 8) {
sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
@@ -1150,7 +1150,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
blorp_nir_discard_if_outside_rect(&b, dst_pos, &v);
}
- src_pos = blorp_blit_apply_transform(&b, nir_i2f(&b, dst_pos), &v);
+ src_pos = blorp_blit_apply_transform(&b, nir_i2f32(&b, dst_pos), &v);
if (dst_pos->num_components == 3) {
/* The sample coordinate is an integer that we want left alone but
* blorp_blit_apply_transform() blindly applies the transform to all
@@ -1175,7 +1175,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
/* Resolves (effecively) use texelFetch, so we need integers and we
* don't care about the sample index if we got one.
*/
- src_pos = nir_f2i(&b, nir_channels(&b, src_pos, 0x3));
+ src_pos = nir_f2i32(&b, nir_channels(&b, src_pos, 0x3));
if (devinfo->gen == 6) {
/* Because gen6 only supports 4x interleved MSAA, we can do all the
@@ -1187,7 +1187,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
*/
src_pos = nir_ishl(&b, src_pos, nir_imm_int(&b, 1));
src_pos = nir_iadd(&b, src_pos, nir_imm_int(&b, 1));
- src_pos = nir_i2f(&b, src_pos);
+ src_pos = nir_i2f32(&b, src_pos);
color = blorp_nir_tex(&b, &v, src_pos, key->texture_data_type);
} else {
/* Gen7+ hardware doesn't automaticaly blend. */
@@ -1204,11 +1204,11 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
} else {
/* We're going to use texelFetch, so we need integers */
if (src_pos->num_components == 2) {
- src_pos = nir_f2i(&b, src_pos);
+ src_pos = nir_f2i32(&b, src_pos);
} else {
assert(src_pos->num_components == 3);
- src_pos = nir_vec3(&b, nir_channel(&b, nir_f2i(&b, src_pos), 0),
- nir_channel(&b, nir_f2i(&b, src_pos), 1),
+ src_pos = nir_vec3(&b, nir_channel(&b, nir_f2i32(&b, src_pos), 0),
+ nir_channel(&b, nir_f2i32(&b, src_pos), 1),
nir_channel(&b, src_pos, 2));
}
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index ef569b5588c..bc1ccfba3d2 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -641,17 +641,17 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
}
switch (instr->op) {
- case nir_op_i2f:
- case nir_op_u2f:
+ case nir_op_i2f32:
+ case nir_op_u2f32:
if (optimize_extract_to_float(instr, result))
return;
inst = bld.MOV(result, op[0]);
inst->saturate = instr->dest.saturate;
break;
- case nir_op_f2d:
- case nir_op_i2d:
- case nir_op_u2d:
+ case nir_op_f2f64:
+ case nir_op_i2f64:
+ case nir_op_u2f64:
/* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
*
* "When source or destination is 64b (...), regioning in Align1
@@ -676,25 +676,15 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
}
/* fallthrough */
- case nir_op_i642d:
- case nir_op_u642d:
+ case nir_op_f2f32:
+ case nir_op_f2i32:
+ case nir_op_f2u32:
case nir_op_f2i64:
case nir_op_f2u64:
- case nir_op_i2i64:
- case nir_op_i2u64:
- case nir_op_u2i64:
- case nir_op_u2u64:
- case nir_op_d2f:
- case nir_op_d2i:
- case nir_op_d2u:
- case nir_op_i642f:
- case nir_op_u642f:
- case nir_op_u2i32:
case nir_op_i2i32:
+ case nir_op_i2i64:
case nir_op_u2u32:
- case nir_op_i2u32:
- case nir_op_f2i:
- case nir_op_f2u:
+ case nir_op_u2u64:
inst = bld.MOV(result, op[0]);
inst->saturate = instr->dest.saturate;
break;
@@ -1077,7 +1067,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
inst->saturate = instr->dest.saturate;
break;
- case nir_op_b2i64:
case nir_op_b2i:
case nir_op_b2f:
bld.MOV(result, negate(op[0]));
@@ -1085,14 +1074,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_i2b:
case nir_op_f2b:
- case nir_op_i642b:
- case nir_op_d2b:
if (nir_src_bit_size(instr->src[0].src) == 64) {
/* two-argument instructions can't take 64-bit immediates */
fs_reg zero;
fs_reg tmp;
- if (instr->op == nir_op_d2b) {
+ if (instr->op == nir_op_f2b) {
zero = vgrf(glsl_type::double_type);
tmp = vgrf(glsl_type::double_type);
} else {
diff --git a/src/intel/compiler/brw_nir_attribute_workarounds.c b/src/intel/compiler/brw_nir_attribute_workarounds.c
index d695771f04a..c719371ddf1 100644
--- a/src/intel/compiler/brw_nir_attribute_workarounds.c
+++ b/src/intel/compiler/brw_nir_attribute_workarounds.c
@@ -99,7 +99,7 @@ apply_attr_wa_block(nir_block *block, struct attr_wa_state *state)
nir_imm_vec4(b, 1.0f / ((1 << 9) - 1), 1.0f / ((1 << 9) - 1),
1.0f / ((1 << 9) - 1), 1.0f / ((1 << 1) - 1));
val = nir_fmax(b,
- nir_fmul(b, nir_i2f(b, val), es3_normalize_factor),
+ nir_fmul(b, nir_i2f32(b, val), es3_normalize_factor),
nir_imm_float(b, -1.0f));
} else {
/* The following equations are from the OpenGL 3.2 specification:
@@ -121,18 +121,18 @@ apply_attr_wa_block(nir_block *block, struct attr_wa_state *state)
/* For signed normalization, the numerator is 2c+1. */
nir_ssa_def *two = nir_imm_float(b, 2.0f);
nir_ssa_def *one = nir_imm_float(b, 1.0f);
- val = nir_fadd(b, nir_fmul(b, nir_i2f(b, val), two), one);
+ val = nir_fadd(b, nir_fmul(b, nir_i2f32(b, val), two), one);
} else {
/* For unsigned normalization, the numerator is just c. */
- val = nir_u2f(b, val);
+ val = nir_u2f32(b, val);
}
val = nir_fmul(b, val, normalize_factor);
}
}
if (wa_flags & BRW_ATTRIB_WA_SCALE) {
- val = (wa_flags & BRW_ATTRIB_WA_SIGN) ? nir_i2f(b, val)
- : nir_u2f(b, val);
+ val = (wa_flags & BRW_ATTRIB_WA_SIGN) ? nir_i2f32(b, val)
+ : nir_u2f32(b, val);
}
nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, nir_src_for_ssa(val),
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index ca2e5dd05eb..23842653997 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -1287,32 +1287,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_vec4:
unreachable("not reached: should be handled by lower_vec_to_movs()");
- case nir_op_i2f:
- case nir_op_u2f:
+ case nir_op_i2f32:
+ case nir_op_u2f32:
inst = emit(MOV(dst, op[0]));
inst->saturate = instr->dest.saturate;
break;
- case nir_op_f2i:
- case nir_op_f2u:
- inst = emit(MOV(dst, op[0]));
- break;
-
- case nir_op_d2f:
- emit_conversion_from_double(dst, op[0], instr->dest.saturate);
- break;
-
- case nir_op_f2d:
- emit_conversion_to_double(dst, op[0], instr->dest.saturate);
- break;
-
- case nir_op_d2i:
- case nir_op_d2u:
- emit_conversion_from_double(dst, op[0], instr->dest.saturate);
+ case nir_op_f2f32:
+ case nir_op_f2i32:
+ case nir_op_f2u32:
+ if (nir_src_bit_size(instr->src[0].src) == 64)
+ emit_conversion_from_double(dst, op[0], instr->dest.saturate);
+ else
+ inst = emit(MOV(dst, op[0]));
break;
- case nir_op_i2d:
- case nir_op_u2d:
+ case nir_op_f2f64:
+ case nir_op_i2f64:
+ case nir_op_u2f64:
emit_conversion_to_double(dst, op[0], instr->dest.saturate);
break;
@@ -1681,26 +1673,25 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
break;
case nir_op_f2b:
- emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
- break;
-
- case nir_op_d2b: {
- /* We use a MOV with conditional_mod to check if the provided value is
- * 0.0. We want this to flush denormalized numbers to zero, so we set a
- * source modifier on the source operand to trigger this, as source
- * modifiers don't affect the result of the testing against 0.0.
- */
- src_reg value = op[0];
- value.abs = true;
- vec4_instruction *inst = emit(MOV(dst_null_df(), value));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ if (nir_src_bit_size(instr->src[0].src) == 64) {
+ /* We use a MOV with conditional_mod to check if the provided value is
+ * 0.0. We want this to flush denormalized numbers to zero, so we set a
+ * source modifier on the source operand to trigger this, as source
+ * modifiers don't affect the result of the testing against 0.0.
+ */
+ src_reg value = op[0];
+ value.abs = true;
+ vec4_instruction *inst = emit(MOV(dst_null_df(), value));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
- src_reg one = src_reg(this, glsl_type::ivec4_type);
- emit(MOV(dst_reg(one), brw_imm_d(~0)));
- inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0));
- inst->predicate = BRW_PREDICATE_NORMAL;
+ src_reg one = src_reg(this, glsl_type::ivec4_type);
+ emit(MOV(dst_reg(one), brw_imm_d(~0)));
+ inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ } else {
+ emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
+ }
break;
- }
case nir_op_i2b:
emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ));
diff --git a/src/intel/vulkan/anv_nir_lower_input_attachments.c b/src/intel/vulkan/anv_nir_lower_input_attachments.c
index 244e7ff7ae1..6ed7fafbf01 100644
--- a/src/intel/vulkan/anv_nir_lower_input_attachments.c
+++ b/src/intel/vulkan/anv_nir_lower_input_attachments.c
@@ -57,7 +57,7 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
nir_builder_init(&b, impl);
b.cursor = nir_before_instr(&load->instr);
- nir_ssa_def *frag_coord = nir_f2i(&b, load_frag_coord(&b));
+ nir_ssa_def *frag_coord = nir_f2i32(&b, load_frag_coord(&b));
nir_ssa_def *offset = nir_ssa_for_src(&b, load->src[0], 2);
nir_ssa_def *pos = nir_iadd(&b, frag_coord, offset);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 11:22:05 +0000